WCET 2014
Date: Jul 08, 2014 1:00 am – Jul 08, 2014 11:00 am
Location: Madrid, Spain
The 14th International Workshop on Worst-Case Execution Time Analysis (WCET
2014) will take place in conjunction with the Euromicro Conference on Real- Time Systems (ECRTS 2014) at Madrid, Spain.
WCET 2014 is kindly supported by TACLe (www.tacle.eu), a European COST-Action on Timing Analysis on Code-Level.
GOALS AND TOPICS
A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori. Perhaps paradoxically, this problem has become more difficult by the introduction of performance-enhancing architectural elements, such as caches, pipelines, and multi-threading, which introduce a large degree of uncertainty and make timing guarantees harder to provide.
The WCET workshop focuses on the analysis and design of timing-predictable systems, with a strong emphasis on worst-case execution time (WCET) analysis.
Topics of interest include all aspects of timing analysis and timing-predictability. This includes (but is not limited to):
- WCET analysis for multi-threaded and multi-core systems
- Low-level timing analysis, modeling and analysis of processor features
- Flow analysis for WCET, loop bounds, infeasible paths
- Measurement-based WCET analysis
- Different approaches to WCET computation
- Probabilistic timing analysis
- Tools for WCET analysis
- Integration of WCET and schedulability analysis
- Integration of WCET analysis in development processes
- Strategies to reduce the complexity of WCET analysis
- Program and processor design for timing predictability
- Compiler-based optimization of worst-case timing
- Timing-predictable, resource-aware operating systems
- Methods and benchmarks for WCET analysis evaluation
- Case studies and industrial experiences of WCET analysis
- WCET analysis in the academic curriculum
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WORKSHOP STRUCTURE
The goal of the workshop is to bring together people from academia, tool vendors and users in industry who are interested in all aspects of timing predictability of real-time systems. The workshop fosters a highly interactive format with ample time for in-depth discussions. It provides a relaxed forum to present and discuss new ideas, new research directions, and to review current trends in this area. The presentations will be kept short to leave plenty of time for interaction of attendees.
This 14th edition of the workshop will feature the presentation of the results of the WCET tool challenge (http://www.irit.fr/wiki/doku.php?id=wtc:start).
GENERAL CHAIR
Heiko Falk Ulm University, DE
PROGRAM COMMITTEE
Sebastian Altmeyer University of Amsterdam, NL
Guillem Bernat Rapita Systems, UK
Francisco J. Cazorla Barcelona Supercomputing Center, ES
Damien Hardy University of Rennes 1 / IRISA, FR
Niklas Holsti Tidorum Ltd., FI
Raimund Kirner University of Hertfordshire, UK
Jens Knoop Vienna University of Technology, AT
Kim G. Larsen Aalborg University, DK
Björn Lisper Mälardalen University, SE
Claire Maiza Grenoble INP/Verimag, FR
Tulika Mitra National University of Singapore, SG
Harini Ramaprasad Southern Illinois University, USA
Jan Reineke Saarland University, DE
Christine Rochange IRIT - Université de Toulouse, FR
Tullio Vardanega University of Padua, IT
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on
The 14th International Workshop on Worst-Case Execution Time Analysis (WCET
2014) will take place in conjunction with the Euromicro Conference on Real- Time Systems (ECRTS 2014) at Madrid, Spain.
WCET 2014 is kindly supported by TACLe (www.tacle.eu), a European COST-Action on Timing Analysis on Code-Level.
GOALS AND TOPICS
A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori. Perhaps paradoxically, this problem has become more difficult by the introduction of performance-enhancing architectural elements, such as caches, pipelines, and multi-threading, which introduce a large degree of uncertainty and make timing guarantees harder to provide.
The WCET workshop focuses on the analysis and design of timing-predictable systems, with a strong emphasis on worst-case execution time (WCET) analysis.
Topics of interest include all aspects of timing analysis and timing-predictability. This includes (but is not limited to):
- WCET analysis for multi-threaded and multi-core systems
- Low-level timing analysis, modeling and analysis of processor features
- Flow analysis for WCET, loop bounds, infeasible paths
- Measurement-based WCET analysis
- Different approaches to WCET computation
- Probabilistic timing analysis
- Tools for WCET analysis
- Integration of WCET and schedulability analysis
- Integration of WCET analysis in development processes
- Strategies to reduce the complexity of WCET analysis
- Program and processor design for timing predictability
- Compiler-based optimization of worst-case timing
- Timing-predictable, resource-aware operating systems
- Methods and benchmarks for WCET analysis evaluation
- Case studies and industrial experiences of WCET analysis
- WCET analysis in the academic curriculum
--------------------------------------------------------------------------------
WORKSHOP STRUCTURE
The goal of the workshop is to bring together people from academia, tool vendors and users in industry who are interested in all aspects of timing predictability of real-time systems. The workshop fosters a highly interactive format with ample time for in-depth discussions. It provides a relaxed forum to present and discuss new ideas, new research directions, and to review current trends in this area. The presentations will be kept short to leave plenty of time for interaction of attendees.
This 14th edition of the workshop will feature the presentation of the results of the WCET tool challenge (http://www.irit.fr/wiki/doku.php?id=wtc:start).
GENERAL CHAIR
Heiko Falk Ulm University, DE
PROGRAM COMMITTEE
Sebastian Altmeyer University of Amsterdam, NL
Guillem Bernat Rapita Systems, UK
Francisco J. Cazorla Barcelona Supercomputing Center, ES
Damien Hardy University of Rennes 1 / IRISA, FR
Niklas Holsti Tidorum Ltd., FI
Raimund Kirner University of Hertfordshire, UK
Jens Knoop Vienna University of Technology, AT
Kim G. Larsen Aalborg University, DK
Björn Lisper Mälardalen University, SE
Claire Maiza Grenoble INP/Verimag, FR
Tulika Mitra National University of Singapore, SG
Harini Ramaprasad Southern Illinois University, USA
Jan Reineke Saarland University, DE
Christine Rochange IRIT - Université de Toulouse, FR
Tullio Vardanega University of Padua, IT