Bringing the Multicore Revolution to Safety-Critical Cyber-Physical Systems
Abstract:
Shared hardware resources like caches and translation look aside buffers (TLBs) introduce timing unpredictability for real-time systems. We propose techniques to mitigate unpredictabil- ity for multicore systems. The TLB improves the performance of the system by caching the virtual page to physical frame mapping. But TLBs present a source of unpredictability for real-rime systems. Standard heap allocated regions do not provide guarantees on the TLB set that will hold a particular page translation. This unpredictability can lead to TLB misses with a penalty of thousands of cycles and consequently intertask interference resulting in loose bounds on the worst case execution time (WCET). In this project, we design and implement a new heap allocator that guarantees the TLB set that will hold a particular page translation. The allocator is based on the concept of page coloring. Virtual pages are colored such that two pages of different color cannot map to the same TLB set. Our experimental evaluations confirm the unpredictability associated with the standard heap allocation. Using a set of synthetic and standard benchmarks, we show that our allocator pro- vides task isolation for real-time tasks. To the best of our knowledge, such TLB isolation is unprecedented, increases TLB predictability and can facilitate WCET analysis. We propose a cache management techniques for mixed-criticality systems. WCET analysis for real-time systems with shared hardware resources is often so pessimistic that the benefit of having multiple cores is negated. In a mixed-criticality system, only highly critical components require conservative provisioning. We design cache management techniques for a mixed-criticality system to increase pre- dictability for timing analysis. Our mixed-criticaility architecture provides temporal isolation across criticality levels. We assign colors to page to control the mapping address of pages in shared caches. We use cache partitioning approach to eliminate interference across processors for levels A and B. Global tasks at level C require tokens to reserve cache lines before loading pages. We implement mixed-criticality on multicore (MC2) scheduler in LITMUSRT. The MC2 scheduler provides budget enforcement using container abstraction to support temporal isolation.
Submitted by Namhoon Kim
on
Abstract:
Shared hardware resources like caches and translation look aside buffers (TLBs) introduce timing unpredictability for real-time systems. We propose techniques to mitigate unpredictabil- ity for multicore systems. The TLB improves the performance of the system by caching the virtual page to physical frame mapping. But TLBs present a source of unpredictability for real-rime systems. Standard heap allocated regions do not provide guarantees on the TLB set that will hold a particular page translation. This unpredictability can lead to TLB misses with a penalty of thousands of cycles and consequently intertask interference resulting in loose bounds on the worst case execution time (WCET). In this project, we design and implement a new heap allocator that guarantees the TLB set that will hold a particular page translation. The allocator is based on the concept of page coloring. Virtual pages are colored such that two pages of different color cannot map to the same TLB set. Our experimental evaluations confirm the unpredictability associated with the standard heap allocation. Using a set of synthetic and standard benchmarks, we show that our allocator pro- vides task isolation for real-time tasks. To the best of our knowledge, such TLB isolation is unprecedented, increases TLB predictability and can facilitate WCET analysis. We propose a cache management techniques for mixed-criticality systems. WCET analysis for real-time systems with shared hardware resources is often so pessimistic that the benefit of having multiple cores is negated. In a mixed-criticality system, only highly critical components require conservative provisioning. We design cache management techniques for a mixed-criticality system to increase pre- dictability for timing analysis. Our mixed-criticaility architecture provides temporal isolation across criticality levels. We assign colors to page to control the mapping address of pages in shared caches. We use cache partitioning approach to eliminate interference across processors for levels A and B. Global tasks at level C require tokens to reserve cache lines before loading pages. We implement mixed-criticality on multicore (MC2) scheduler in LITMUSRT. The MC2 scheduler provides budget enforcement using container abstraction to support temporal isolation.