Time-Predictable Fault Tolerant Computing for Dependable Automotive Cyber-Physical Systems
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Dependable and secure automotive cyber-physical systems (CPSs) are crucial as human’s lives are dependent on them. Many important subsystems in today’s automobiles such as the engine control system and the anti-brake system are hard real-time systems. If the CPUs in those systems have any fault, regardless of transient faults or hard faults, not only the computation results may be wrong, but also the results may be delivered late. Therefore, CPUs used in those systems must be able to handle two tasks: 1) detect and correct the errors, and 2) ensure that the error detection and correction can be done within the deadline so that the system can function correctly or have a grace period.
Microprocessors have been deeply embedded in today’s automobiles. However, due to the advances of computer architectures that are generally focused on improving the average-case performance, many architectural features such as caches and pipelines have made it very hard to safely and accurately predict the worst-case execution time (WCET), which is crucial for ensuring schedulability of hard real-time tasks. Therefore, in light of the dependability against possible transient and hard errors, the CPU itself must be both high performance and time predictable in the fault-free case. Then on top of that, we can study fault-tolerant techniques to maintain the time predictability. Therefore, we propose to study time-predictable fault tolerant techniques based on the Real-time Very Long Instruction Word (RVLIW) processor we designed, which can provide both high performance and time predictability by leveraging the static scheduling and compiler
optimizations [1].
Submitted by Katie Dey
on
pdf
Dependable and secure automotive cyber-physical systems (CPSs) are crucial as human’s lives are dependent on them. Many important subsystems in today’s automobiles such as the engine control system and the anti-brake system are hard real-time systems. If the CPUs in those systems have any fault, regardless of transient faults or hard faults, not only the computation results may be wrong, but also the results may be delivered late. Therefore, CPUs used in those systems must be able to handle two tasks: 1) detect and correct the errors, and 2) ensure that the error detection and correction can be done within the deadline so that the system can function correctly or have a grace period.
Microprocessors have been deeply embedded in today’s automobiles. However, due to the advances of computer architectures that are generally focused on improving the average-case performance, many architectural features such as caches and pipelines have made it very hard to safely and accurately predict the worst-case execution time (WCET), which is crucial for ensuring schedulability of hard real-time tasks. Therefore, in light of the dependability against possible transient and hard errors, the CPU itself must be both high performance and time predictable in the fault-free case. Then on top of that, we can study fault-tolerant techniques to maintain the time predictability. Therefore, we propose to study time-predictable fault tolerant techniques based on the Real-time Very Long Instruction Word (RVLIW) processor we designed, which can provide both high performance and time predictability by leveraging the static scheduling and compiler
optimizations [1].
Submitted by Katie Dey
on