Visible to the public SiGe Clock and Data Recovery System Based on Injection-Locked Oscillator for 100 Gbit/s Serial Data Link

TitleSiGe Clock and Data Recovery System Based on Injection-Locked Oscillator for 100 Gbit/s Serial Data Link
Publication TypeJournal Article
Year of Publication2014
AuthorsBéraud-Sudreau, Q., Begueret, J.-B., Mazouffre, O., Pignol, M., Baguena, L., Neveu, C., Deval, Y., Taris, T.
JournalSolid-State Circuits, IEEE Journal of
Date PublishedSept
Keywords100 Gbps, BiCMOS integrated circuits, BiCMOS SiGe, bit rate 100 Gbit/s, bit rate 50 Gbit/s, CDR system, clock and data recovery (CDR), clock and data recovery circuits, clock and data recovery system, Clocks, comparators (circuits), Detectors, frequency 100 GHz, frequency 25 GHz, frequency tracking, Ge-Si alloys, injection locked oscillators, injection-locked oscillator, injection-locked oscillator (ILO), Logic gates, microwave oscillators, millimeter-wave data communication, Oscillators, phase comparator, Phase locked loops, phase noise, phase tracking, phase-locked loop (PLL), power 1.4 W, serial data link, SiGe, size 130 nm, Synchronization, time 1.2 ps, voltage 2.3 V, Voltage control, windowed phase comparator, zero bit patterns

Clock and data recovery (CDR) systems are the first logic blocks in serial data receivers and the latter's performance depends on the CDR. In this paper, a 100 Gbit/s CDR designed in 130 nm BiCMOS SiGe is presented. The CDR uses an injection locked oscillator (ILO) which delivers the 100 GHz clock. The inherent phase shift between the recovered clock and the incoming data is compensated by a feedback loop which performs phase and frequency tracking. Furthermore, a windowed phase comparator has been used, first to lower the classical number of gates, in order to prevent any delay skews between the different phase detector blocks, then to decrease the phase comparator operating frequency, and furthermore to extend the ability to track zero bit patterns The measurements results demonstrate a 100 GHz clock signal extracted from 50 Gb/s input data, with a phase noise as low as 98 dBc/Hz at 100 kHz offset from the carrier frequency. The rms jitter of the 25 GHz recovered data is only 1.2 ps. The power consumption is 1.4 W under 2.3 V power supply.

Citation Key6808420