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The Third Workshop on Low-Power Dependable Computing (LPDC)

In conjunction with The 7th International Green and Sustainable Computing Conference (IGSC)

** NEWS: IEEE Transactions on Sustainable Computing (T-SUSC) special issue on LPDC Selected top papers from the workshop will be invited to submit to this special issue!


As part of the IEEE-Technically sponsored International Green and Sustainable Computing conference, the workshop on Low-Power Dependable Computing (LPDC) will be organized to address various design aspects of power efficient and dependable computing infrastructures. Dependable computing is normally achieved through various error reduction, detection and recovery techniques at different levels (for instance, circuit, architecture, operating systems, compiler and application software) in the systems. With the continuous technology scaling and miniaturization of computing systems, faults will become more common and it is imperative for most modern computing systems to deploy various fault-tolerance techniques. On the other hand, fault-tolerance does not come for free, and generally has power/energy/temperature implications, which warrants careful consideration since power/energy is the first-class system resource and has been emerging as the limiting factor for multicore scaling.

This workshop aims at establishing a specialized forum for practitioners and researchers from both industry and academia who work on different aspects of fault tolerance and power/energy efficiency to exchange ideas on how to achieve low-power dependable computing. In particular, understanding the interdependencies between reliability and power are important to consider, e.g., high power consumption may lead to elevated temperature that can further aggravate the reliability.

To cover a broad range of research related to energy efficiency and dependable computing, the workshop will consider various levels (from circuits to software), components (from memory to computation) and systems (from battery-powered embedded systems to large scale reliable servers). The topics of interest include, but are not limited to, the following:

  • Energy-efficient redundant circuit design
  • Energy-efficient fault-tolerance architecture
  • Compilation techniques for reliability and low-power
  • Runtime management and scheduling algorithms for energy-efficiency and fault tolerance
  • Case study on low-power dependable systems
  • Emerging paradigms for low-power and dependable computing, for instance, approximate computing, cross-layer design, etc.
  • Mitigating reliability threats (aging, soft errors, process variations) in Dark Silicon chips
  • Low-power reliable memory and storage systems
  • Low-power and reliable on-chip networks and communication

Workshop Organizers and TPC Chairs:

  • Xiaomin Zhu - National University of Defense Technology, China
  • Muhammad Shafique - Karlsruhe Institute of Technology, Germany
  • Dakai Zhu - University of Texas at San Antonio, USA

Technical Program Committee (TPC):

  • Tam Chantem - Utah State University, USA
  • Alireza Ejlali - Sharif University of Technology, Iran
  • Hui Guo - University of New South Wales, Australia
  • Can Hankendi - AMD Inc. Germany
  • Sybille Hellebrand - The University of Paderborn, Germany
  • Houman Homayoun - George Mason University, USA
  • Zheng Li - Western Illinois University, USA
  • Saman Kiamehr - Karlsruhe Institute of Technology, Germany
  • Umit Ogras - Arizona State University, USA
  • Amir Rahmani - University of Turku, Finland
  • Semeen Rehman -Dresden University of Technology (TUD), Germany
  • Mohammad Sabry - Stanford University, USA
  • Jurgen Teich - Friedrich-Alexander University (FAU), Germany
  • Sara Vinco - The Polytechnic University of Turin, Italy
  • Tongquan Wei - East China Normal University, China
  • Chengmo Yang - University of Delaware, USA
Event Details
Hangzhou, China