Visible to the public Deadline Extended (Jan 24): Work in Progress session of RTAS'17Conflict Detection Enabled

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CALL FOR WiP PAPERS - Deadline Extended (Jan 24)

The 23rd IEEE Real-Time Embedded Technology & Applications Symposium Work-in-Progress Session (RTAS-WIP 2017)

18 April, 2017 - Pittsburgh, PA, USA

The Work-in-Progress (WiP) session at RTAS 2017 is dedicated to new and on-going research in the field of real-time and embedded systems. Authors are invited to submit short papers describing ongoing, unpublished work in all areas of real-time and embedded technology, including applications, systems, tools, methodologies, foundations, wireless sensor networks, and hardware-software co-design. In keeping with the spirit of the main symposium, submissions with an emphasis on systems and application aspects are especially encouraged.

The WiP session provides researchers and developers with an opportunity to discuss evolving and early-stage ideas, new research directions, to review current trends in the area and to receive feedback from the real-time systems community at large.

Accepted papers will be published in the same proceedings as the main conference (no longer a separate booklet) and are indexed by IEEE (they receive a DOI and appear in IEEExplore). All submissions should be in the form of short papers of 2 to 4 pages in the IEEE 10-point, two-column conference format, including all references and appendices. Titles should be in the format "Work-in-Progress: WiP_Title".

Authors of accepted papers are expected to give a brief presentation in the work-in-progress session of the conference and also showcase their work at the poster session. By submitting a paper, the authors agree that, if accepted, at least one author will register for the conference and present the work in person at the Work-in-Progress session.

Important dates:

Submission: Jan 24, 2017 (extended)
Notifications: Feb 5, 2017
Camera ready: Feb 10, 2017

Topics of particular interest include, but are not limited to:

  • Applications and case studies
  • Time-Sensitive Networks (TSN) simulations and analysis
  • Runtime environment, OS, and middleware
  • Adaptive systems
  • Analysis, simulation, and debugging tools
  • Cloud and distributed computing
  • Composition and component-based systems
  • Computer architectures and microprocessors
  • Formal methods
  • Hardware/software co-design
  • Many-core systems
  • Multi-criticality systems
  • Multicore and GPU computing
  • Power-, thermal-, and energy-aware computing
  • Programming languages and compilers
  • Real-time databases
  • Scheduling and schedulability analysis
  • SOCs, FPGAs, and reconfigurable systems
  • Software engineering
  • Execution-time analysis (static, measurement-based, and probabilistic)
  • Statistical and Probabilistic tools for analysis/simulating real-time systems
  • Storage systems
  • Synchronization
  • System synthesis and optimization
  • Testing, validation, and certification
  • Virtualization and isolation
  • Wireless communications
  • Tools

Program Committee

  • Dorin Maxim, University of Lorraine/Loria, Nancy, France (Chair)
  • Yasmina Abdeddaim, ESIEE, LIGM, France
  • Kunal Agrawal, Washington University in St. Louis, USA
  • Antoine Bertout, Inria de Paris, France
  • Armelle Bonenfant, IRIT, France
  • Silviu Craciunas, TTTech Computertechnik, Austria
  • Benjamin Lesage, University of York, UK
  • Geoffrey Nellissen, Cister, ISEP, Portugal
  • Florian Polzlbauer, Virtual Vehicle, Austria
  • Abhilash Thekkilakattil, Malardalen University, Sweden
  • Franck Wartel, Airbus Defense and Space, France

Please contact with any questions you may have.