Visible to the public "Improved serial 2D-DWT processor for advanced encryption standard"Conflict Detection Enabled

Title"Improved serial 2D-DWT processor for advanced encryption standard"
Publication TypeConference Paper
Year of Publication2015
AuthorsK. R. Kashwan, K. A. Dattathreya
Conference Name2015 IEEE International Conference on Computer Graphics, Vision and Information Security (CGVIS)
Date PublishedNov
Keywordsadvanced encryption standard, AES, application specific integrated circuits, ASIC circuit design, CMOS technology, compression ratio, cryptography, data compression, discrete wavelet transform, discrete wavelet transforms, DWT, Encryption, frequency 333 MHz, Hardware, high speed encryption, Image coding, image data security, lifting scheme algorithm, low power ASIC, pubcrawl170102, Quantization (signal), RTL-GDSII, secured image processing, serial 2D-DWT processor, serialized DT processor, size 65 nm

This paper reports a research work on how to transmit a secured image data using Discrete Wavelet Transform (DWT) in combination of Advanced Encryption Standard (AES) with low power and high speed. This can have better quality secured image with reduced latency and improved throughput. A combined model of DWT and AES technique help in achieving higher compression ratio and simultaneously it provides high security while transmitting an image over the channels. The lifting scheme algorithm is realized using a single and serialized DT processor to compute up to 3-levels of decomposition for improving speed and security. An ASIC circuit is designed using RTL-GDSII to simulate proposed technique using 65 nm CMOS Technology. The ASIC circuit is implemented on an average area of about 0.76 mm2 and the power consumption is estimated in the range of 10.7-19.7 mW at a frequency of 333 MHz which is faster compared to other similar research work reported.

Citation Key7449923