Visible to the public "Fault Detection and Correction in Processing AES Encryption Algorithm"Conflict Detection Enabled

Title"Fault Detection and Correction in Processing AES Encryption Algorithm"
Publication TypeConference Paper
Year of Publication2015
AuthorsM. Ayoob, W. Adi
Conference Name2015 Sixth International Conference on Emerging Security Technologies (EST)
Date PublishedSept
ISBN Number978-1-4673-9799-5
Accession Number15838935
Keywordsadvanced encryption standard, AES cipher, AES encryption algorithm, AES Encryption process, AES linear mappings and error correcting codes, AES round structure, Ciphers, cryptography, cryptosystem, ECC properties, Encryption, error control mechanisms, error correction, error detection, error syndrome, Execution errors and countermeasure against fault injection side channel attacks, fault correction technique, fault coverage, fault detection, Fault detection and correction, fault detection technique, fault diagnosis, fault injection attack, fault-tolerance technique design, field programmable gate arrays, FPGA technology, Hardware, linear mappings, MC transformation, MixColumn transformation, noise effects, production faults, pubcrawl170102, radiation effect, ShiftRow transformation, side-channel attacks, Single event upsets, SR transformation, system reliability improvement, system security improvement, temporary redundant check words

Robust and stringent fault detection and correction techniques in executing Advanced Encryption Standard (AES) are still interesting issues for many critical applications. The purpose of fault detection and correction techniques is not only to ensure the reliability of a cryptosystem, but also protect the system against side channel attacks. Such errors could result due to a fault injection attack, production faults, noise or radiation effects in deep space. Devising a proper error control mechanisms for AES cipher during execution would improve both system reliability and security. In this work a novel fault detection and correction algorithm is proposed. The proposed mechanism is making use of the linear mappings of AES round structure to detect errors in the ShiftRow (SR) and MixColumn (MC) transformations. The error correction is achieved by creating temporary redundant check words through the combined SR and MC mapping to create in case of errors an error syndrome leading to error correction with relatively minor additional complexity. The proposed technique is making use of an error detecting and correcting capability in the combined mapping of SR and MC rather than detecting and/or correcting errors in each transformation separately. The proposed technique is making use especially of the MC mapping exhibiting efficient ECC properties, which can be deployed to simplify the design of a fault-tolerance technique. The performance of the algorithm proposed is evaluated by a simulated system model in FPGA technology. The simulation results demonstrate the ability to reach relatively high fault coverage with error correction up to four bytes of execution errors in the merged transformation SR-MC. The overall gate complexity overhead of the resulting system is estimated for proposed technique in FPGA technology.

Citation Key7429263