Visible to the public "Development of platform using NIOS II soft core processor for image encryption and decryption using AES algorithm"Conflict Detection Enabled

Title"Development of platform using NIOS II soft core processor for image encryption and decryption using AES algorithm"
Publication TypeConference Paper
Year of Publication2015
AuthorsS. V. Trivedi, M. A. Hasamnis
Conference Name2015 International Conference on Communications and Signal Processing (ICCSP)
Date PublishedApril
ISBN Number978-1-4799-8081-9
Accession Number15600093
Keywordsadvanced encryption standard, Advanced Encryption Standard (AES) Algorithm, AES encryption algorithm, Algorithm design and analysis, Altera DE2 FPGA board, computer network security, confidential image data protection, cryptography, Cyclone II EP2C35F672, Cyclone II FPGA, data compression, data storage, Data Transmission, digital communication network, digital data exchange cryptography, digital world Internet, discrete wavelet transform, DWT, Encryption, field programmable gate arrays, Image coding, image compression, image decryption, image encryption, information transmission, Internet, MATLAB, microprocessor chips, Network security, NIOS II soft core processor, pubcrawl170102, QUARTUS II, scrambling plaintext, SOPC builder tool, Standards, system-on-chip, system-on-programmable chip builder tool, W7 key stream generator

In our digital world internet is a widespread channel for transmission of information. Information that is transmitted can be in form of messages, images, audios and videos. Due to this escalating use of digital data exchange cryptography and network security has now become very important in modern digital communication network. Cryptography is a method of storing and transmitting data in a particular form so that only those for whom it is intended can read and process it. The term cryptography is most often associated with scrambling plaintext into ciphertext. This process is called as encryption. Today in industrial processes images are very frequently used, so it has become essential for us to protect the confidential image data from unauthorized access. In this paper Advanced Encryption Standard (AES) which is a symmetric algorithm is used for encryption and decryption of image. Performance of Advanced Encryption Standard algorithm is further enhanced by adding a key stream generator W7. NIOS II soft core processor is used for implementation of encryption and decryption algorithm. A system is designed with the help of SOPC (System on programmable chip) builder tool which is available in QUARTUS II (Version 10.1) environment using NIOS II soft core processor. Developed single core system is implemented using Altera DE2 FPGA board (Cyclone II EP2C35F672). Using MATLAB the image is read and then by using DWT (Discrete Wavelet Transform) the image is compressed. The image obtained after compression is now given as input to proposed AES encryption algorithm. The output of encryption algorithm is given as input to decryption algorithm in order to get back the original image. The implementation of which is done on the developed single core platform using NIOS II processor. Finally the output is analyzed in MATLAB by plotting histogram of original and encrypted image.

Citation Key7322684