Visible to the public An efficient hardware implementation of few lightweight block cipher

TitleAn efficient hardware implementation of few lightweight block cipher
Publication TypeConference Paper
Year of Publication2015
AuthorsNemati, A., Feizi, S., Ahmadi, A., Haghiri, S., Ahmadi, M., Alirezaee, S.
Conference Name2015 The International Symposium on Artificial Intelligence and Signal Processing (AISP)
Date PublishedMarch 2015
ISBN Number978-1-4799-8818-1
KeywordsAlgorithm design and analysis, Block Cipher, Ciphers, cryptography, Encryption, Feistel structure, FeW Algorithm, FeW cryptography algorithm, FeW lightweight block cipher, Field Programmable Gate Array (FPGA), field programmable gate arrays, FPGA, Hardware, Hardware Implementation, high level synthesis, pubcrawl170112, radio-frequency identification, radiofrequency identification, resource-efficient cryptographic incipient, RFID, Schedules, security system, sensor node

Radio-frequency identification (RFID) are becoming a part of our everyday life with a wide range of applications such as labeling products and supply chain management and etc. These smart and tiny devices have extremely constrained resources in terms of area, computational abilities, memory, and power. At the same time, security and privacy issues remain as an important problem, thus with the large deployment of low resource devices, increasing need to provide security and privacy among such devices, has arisen. Resource-efficient cryptographic incipient become basic for realizing both security and efficiency in constrained environments and embedded systems like RFID tags and sensor nodes. Among those primitives, lightweight block cipher plays a significant role as a building block for security systems. In 2014 Manoj Kumar et al proposed a new Lightweight block cipher named as FeW, which are suitable for extremely constrained environments and embedded systems. In this paper, we simulate and synthesize the FeW block cipher. Implementation results of the FeW cryptography algorithm on a FPGA are presented. The design target is efficiency of area and cost.

Citation Keynemati_efficient_2015