Visible to the public Secure Model Checkers for Network-on-Chip (NoC) Architectures

TitleSecure Model Checkers for Network-on-Chip (NoC) Architectures
Publication TypeConference Paper
Year of Publication2016
AuthorsBoraten, Travis, DiTomaso, Dominic, Kodi, Avinash Karanth
Conference NameProceedings of the 26th Edition on Great Lakes Symposium on VLSI
Conference LocationNew York, NY, USA
ISBN Number978-1-4503-4274-2
Keywordscomposability, hardware security, hardware trojan, network on chip, network on chip security, Network Security Architecture, network-on-chip, pubcrawl, Resiliency, Scalability, trojan horse detection

As chip multiprocessors (CMPs) are becoming more susceptible to process variation, crosstalk, and hard and soft errors, emerging threats from rogue employees in a compromised foundry are creating new vulnerabilities that could undermine the integrity of our chips with malicious alterations. As the Network-on-Chip (NoC) is a focal point of sensitive data transfer and critical device coordination, there is an urgent demand for secure and reliable communication. In this paper we propose Secure Model Checkers (SMCs), a real-time solution for control logic verification and functional correctness in the micro-architecture to detect Hardware Trojan (HT) induced denial-of-service attacks and improve reliability. In our evaluation, we show that SMCs provides significant security enhancements in real-time with only 1.5% power and 1.1% area overhead penalty in the micro-architecture.

Citation Keyboraten_secure_2016