Visible to the public A flexible system-on-a-chip implementation of the Advanced Encryption Standard

TitleA flexible system-on-a-chip implementation of the Advanced Encryption Standard
Publication TypeConference Paper
Year of Publication2016
AuthorsCarnevale, B., Baldanzi, L., Pilato, L., Fanucci, L.
Conference Name2016 20th International Conference on System Theory, Control and Computing (ICSTCC)
Date Publishedoct
Keywordsadvanced encryption standard, advanced peripheral bus, AES, CBC, cipher block chaining mode, Clocks, complex electronic systems, composability, cryptography, Encryption, encryption algorithm, field programmable gate arrays, flexible interface, flexible system-on-a-chip, hardware-software approach, network on chip, network on chip security, Network security, peripheral interfaces, processor, pubcrawl, Registers, Resiliency, resource usage, Scalability, security, Standards, symmetric encryption, System-on-a-chip, system-on-chip, Xilinx Zynq 7000
AbstractSystems-on-a-Chip are among the best-performing and complete solutions for complex electronic systems. This is also true in the field of network security, an application requiring high performance with low resource usage. This work presents an Advanced Encryption Standard implementation for Systems-on-a-Chip using as a reference the Cipher Block Chaining mode. In particular, a flexible interface based and the Advanced Peripheral Bus to integrate the encryption algorithm with any kind of processor is presented. The hardware-software approach of the architecture is also analyzed and described. The final system was integrated on a Xilinx Zynq 7000 to prototype and evaluate the idea. Results show that our solution demonstrates good performance and flexibility with low resource usage, occupying less than 2% of the Zynq 7000 with a throughput of 320 Mbps. The architecture is suitable when implementations of symmetric encryption algorithms for modern Systems-on-a-Chip are required.
Citation Keycarnevale_flexible_2016