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Liu, M., Zhou, C., Tang, Q., Parhi, K. K., Kim, C. H..  2017.  A data remanence based approach to generate 100% stable keys from an SRAM physical unclonable function. 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED). :1–6.

The start-up value of an SRAM cell is unique, random, and unclonable as it is determined by the inherent process mismatch between transistors. These properties make SRAM an attractive circuit for generating encryption keys. The primary challenge for SRAM based key generation, however, is the poor stability when the circuit is subject to random noise, temperature and voltage changes, and device aging. Temporal majority voting (TMV) and bit masking were used in previous works to identify and store the location of unstable or marginally stable SRAM cells. However, TMV requires a long test time and significant hardware resources. In addition, the number of repetitive power-ups required to find the most stable cells is prohibitively high. To overcome the shortcomings of TMV, we propose a novel data remanence based technique to detect SRAM cells with the highest stability for reliable key generation. This approach requires only two remanence tests: writing `1' (or `0') to the entire array and momentarily shutting down the power until a few cells flip. We exploit the fact that the cells that are easily flipped are the most robust cells when written with the opposite data. The proposed method is more effective in finding the most stable cells in a large SRAM array than a TMV scheme with 1,000 power-up tests. Experimental studies show that the 256-bit key generated from a 512 kbit SRAM using the proposed data remanence method is 100% stable under different temperatures, power ramp up times, and device aging.

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Lin, X., Zhang, Z., Chen, M., Sun, Y., Li, Y., Liu, M., Wang, Y., Liu, M..  2020.  GDGCA: A Gene Driven Cache Scheduling Algorithm in Information-Centric Network. 2020 IEEE 3rd International Conference on Information Systems and Computer Aided Education (ICISCAE). :167–172.
The disadvantages and inextensibility of the traditional network require more novel thoughts for the future network architecture, as for ICN (Information-Centric Network), is an information centered and self-caching network, ICN is deeply rooted in the 5G era, of which concept is user-centered and content-centered. Although the ICN enables cache replacement of content, an information distribution scheduling algorithm is still needed to allocate resources properly due to its limited cache capacity. This paper starts with data popularity, information epilepsy and other data related attributes in the ICN environment. Then it analyzes the factors affecting the cache, proposes the concept and calculation method of Gene value. Since the ICN is still in a theoretical state, this paper describes an ICN scenario that is close to the reality and processes a greedy caching algorithm named GDGCA (Gene Driven Greedy Caching Algorithm). The GDGCA tries to design an optimal simulation model, which based on the thoughts of throughput balance and satisfaction degree (SSD), then compares with the regular distributed scheduling algorithm in related research fields, such as the QoE indexes and satisfaction degree under different Poisson data volumes and cycles, the final simulation results prove that GDGCA has better performance in cache scheduling of ICN edge router, especially with the aid of Information Gene value.
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Liu, M., Yan, Y. J., Li, W..  2017.  Implementation and optimization of A5-1 algorithm on coarse-grained reconfigurable cryptographic logic array. 2017 IEEE 12th International Conference on ASIC (ASICON). :279–282.

A5-1 algorithm is a stream cipher used to encrypt voice data in GSM, which needs to be realized with high performance due to real-time requirements. Traditional implementation on FPGA or ASIC can't obtain a trade-off among performance, cost and flexibility. To this aim, this paper introduces CGRCA to implement A5-1, and in order to optimize the performance and resource consumption, this paper proposes a resource-based path seeking (RPS) algorithm to develop an advanced implementation. Experimental results show that final optimal throughput of A5-1 implemented on CGRCA is 162.87Mbps when the frequency is 162.87MHz, and the set-up time is merely 87 cycles, which is optimal among similar works.

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Wang, Y., Huang, F., Hu, Y., Cao, R., Shi, T., Liu, Q., Bi, L., Liu, M..  2018.  Proton Radiation Effects on Y-Doped HfO2-Based Ferroelectric Memory. IEEE Electron Device Letters. 39:823–826.
In this letter, ferroelectric memory performance of TiN/Y-doped-HfO2 (HYO)/TiN capacitors is investigated under proton radiation with 3-MeV energy and different fluence (5e13, 1e14, 5e14, and 1e15 ions/cm2). X-ray diffraction patterns confirm that the orthorhombic phase Pbc21 of HYOfilm has no obvious change after proton radiation. Electrical characterization results demonstrate slight variations of the permittivity and ferroelectric hysteresis loop after proton radiation. The remanent polarization (2Pr) of the capacitor decreases with increasing proton fluence. But the decreasing trend of 2Pr is suppressed under high electric fields. Furthermore, the 2Pr degradation with cycling is abated by proton radiation. These results show that the HYO-based ferroelectric memory is highly resistive to proton radiation, which is potentially useful for space applications.