Visible to the public Biblio

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Hazari, N. A., Alsulami, F., Niamat, M..  2018.  FPGA IP Obfuscation Using Ring Oscillator Physical Unclonable Function. NAECON 2018 - IEEE National Aerospace and Electronics Conference. :105–108.
IP piracy, reverse engineering, and tampering with FPGA based IP is increasing over time. ROPUF based IP obfuscation can provide a feasible solution. In this paper, a novel approach of FPGA IP obfuscation is implemented using Ring Oscillator based Physical Unclonable Function (ROPUF) and random logic gates. This approach provides a lock and key mechanism as well as authentication of FPGA based designs to protect from security threats. Using the Xilinx ISE design tools and ISCAS 89 benchmarks we have designed a secure FPGA based IP protection scheme with an average of 15% area and 10% of power overhead.
Pundir, N., Hazari, N. A., Amsaad, F., Niamat, M..  2017.  A Novel Hybrid Delay Based Physical Unclonable Function Immune to Machine Learning Attacks. 2017 IEEE National Aerospace and Electronics Conference (NAECON). :84–87.

In this paper, machine learning attacks are performed on a novel hybrid delay based Arbiter Ring Oscillator PUF (AROPUF). The AROPUF exhibits improved results when compared to traditional Arbiter Physical Unclonable Function (APUF). The challenge-response pairs (CRPs) from both PUFs are fed to the multilayered perceptron model (MLP) with one hidden layer. The results show that the CRPs generated from the proposed AROPUF has more training and prediction errors when compared to the APUF, thus making it more difficult for the adversary to predict the CRPs.