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Lokananta, F., Hartono, D., Tang, C. M..  2017.  A Scalable and Reconfigurable Verification and Benchmark Environment for Network on Chip Architecture. 2017 4th International Conference on New Media Studies (CONMEDIA). :6–10.

To reduce the complex communication problem that arise as the number of on-chip component increases, the use of Network-on-Chip (NoC) as interconnection architectures have become more promising to solve complex on-chip communication problems. However, providing a suitable test base to measure and verify functionality of any NoC is a compulsory. Universal Verification Methodology (UVM) is introduced as a standardized and reusable methodology for verifying integrated circuit design. In this research, a scalable and reconfigurable verification and benchmark environment for NoC is proposed.