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Brasser, Ferdinand, Davi, Lucas, Dhavlle, Abhijitt, Frassetto, Tommaso, Dinakarrao, Sai Manoj Pudukotai, Rafatirad, Setareh, Sadeghi, Ahmad-Reza, Sasan, Avesta, Sayadi, Hossein, Zeitouni, Shaza et al..  2018.  Advances and Throwbacks in Hardware-assisted Security: Special Session. Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems. :15:1–15:10.
Hardware security architectures and primitives are becoming increasingly important in practice providing trust anchors and trusted execution environment to protect modern software systems. Over the past two decades we have witnessed various hardware security solutions and trends from Trusted Platform Modules (TPM), performance counters for security, ARM's TrustZone, and Physically Unclonable Functions (PUFs), to very recent advances such as Intel's Software Guard Extension (SGX). Unfortunately, these solutions are rarely used by third party developers, make strong trust assumptions (including in manufacturers), are too expensive for small constrained devices, do not easily scale, or suffer from information leakage. Academic research has proposed a variety of solutions, in hardware security architectures, these advancements are rarely deployed in practice.
Sasan, Avesta, Zu, Qi, Wamg, Yanzhi, Seo, Jae-sun, Mohsenin, Tinoosh.  2018.  Low Power and Trusted Machine Learning. Proceedings of the 2018 on Great Lakes Symposium on VLSI. :515–515.

In this special discussion session on machine learning, the panel members discuss various issues related to building secure and low power neuromorphic systems. The security of neuromorphic systems may be discussed in term of the reliability of the model, trust in the model, and security of the underlying hardware. The low power aspect of neuromorphic computing systems may be discussed in terms of adaptation of new devices and technologies, the adaptation of new computational models, development of heterogeneous computing frameworks, or dedicated engines for processing neuromorphic models. This session may include discussion on the design space of such supporting hardware, exploring tradeoffs between power/energy, security, scalability, hardware area, performance, and accuracy.

Roshanisefat, Shervin, Mardani Kamali, Hadi, Sasan, Avesta.  2018.  SRCLock: SAT-Resistant Cyclic Logic Locking for Protecting the Hardware. Proceedings of the 2018 on Great Lakes Symposium on VLSI. :153-158.

In this paper, we claim that cyclic obfuscation, when properly implemented, poses exponential complexity on SAT or CycSAT attack. The CycSAT, in order to generate the necessary cycle avoidance clauses, uses a pre-processing step. We show that this pre-processing step has to compose its cycle avoidance condition on all cycles in a netlist, otherwise, a missing cycle could trap the SAT solver in an infinite loop or force it to return an incorrect key. Then, we propose several techniques by which the number of cycles is exponentially increased with respect to the number of inserted feedbacks. We further illustrate that when the number of feedbacks is increased, the pre-processing step of CycSAT faces an exponential increase in complexity and runtime, preventing the correct composition of loop avoidance clauses in a reasonable time before invoking the SAT solver. On the other hand, if the pre-processing is not completed properly, the SAT solver will get stuck or return incorrect key. Hence, when the cyclic obfuscation in accordance to the conditions proposed in this paper is implemented, it would impose an exponential complexity with respect to the number of inserted feedback, even when the CycSAT solution is used.