Visible to the public Biblio

Filters: Author is K. R. Kashwan  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
K. R. Kashwan, K. A. Dattathreya.  2015.  "Improved serial 2D-DWT processor for advanced encryption standard". 2015 IEEE International Conference on Computer Graphics, Vision and Information Security (CGVIS). :209-213.

This paper reports a research work on how to transmit a secured image data using Discrete Wavelet Transform (DWT) in combination of Advanced Encryption Standard (AES) with low power and high speed. This can have better quality secured image with reduced latency and improved throughput. A combined model of DWT and AES technique help in achieving higher compression ratio and simultaneously it provides high security while transmitting an image over the channels. The lifting scheme algorithm is realized using a single and serialized DT processor to compute up to 3-levels of decomposition for improving speed and security. An ASIC circuit is designed using RTL-GDSII to simulate proposed technique using 65 nm CMOS Technology. The ASIC circuit is implemented on an average area of about 0.76 mm2 and the power consumption is estimated in the range of 10.7-19.7 mW at a frequency of 333 MHz which is faster compared to other similar research work reported.