Visible to the public Design of Boolean Chaotic Oscillator Using CMOS Technology for True Random Number Generation

TitleDesign of Boolean Chaotic Oscillator Using CMOS Technology for True Random Number Generation
Publication TypeConference Paper
Year of Publication2017
AuthorsRajagopalan, S., Rethinam, S., Deepika, A. N., Priyadarshini, A., Jyothirmai, M., Rengarajan, A.
Conference Name2017 International Conference on Microelectronic Devices, Circuits and Systems (ICMDCS)
Date Publishedaug
Keywords45nm CMOS technology, application specific integrated circuits, authentication security, cadence virtuoso, Cadence Virtuoso tool, Capacitors, chaos, CMOS, CMOS Boolean Chaotic Oscillator Design, CMOS integrated circuits, cryptography, data transmission security, delays, Generators, Human Behavior, Inverters, Logic gates, message authentication, Metrics, National Institute of Standards and Technology, NI ELVIS platform, Oscillators, pubcrawl, random cryptographic keys, random key generation, random number generation, random number generators, random numbers, resilience, Resiliency, Ring oscillators, Scalability, security keys
Abstract

True random numbers have a fair role in modern digital transactions. In order to achieve secured authentication, true random numbers are generated as security keys which are highly unpredictable and non-repetitive. True random number generators are used mainly in the field of cryptography to generate random cryptographic keys for secure data transmission. The proposed work aims at the generation of true random numbers based on CMOS Boolean Chaotic Oscillator. As a part of this work, ASIC approach of CMOS Boolean Chaotic Oscillator is modelled and simulated using Cadence Virtuoso tool based on 45nm CMOS technology. Besides, prototype model has been implemented with circuit components and analysed using NI ELVIS platform. The strength of the generated random numbers was ensured by NIST (National Institute of Standards and Technology) Test Suite and ASIC approach was validated through various parameters by performing various analyses such as frequency, delay and power.

URLhttps://ieeexplore.ieee.org/document/8211590
DOI10.1109/ICMDCS.2017.8211590
Citation Keyrajagopalan_design_2017