Visible to the public PCH framework for IP runtime security verification

TitlePCH framework for IP runtime security verification
Publication TypeConference Paper
Year of Publication2017
AuthorsGuo, X., Dutta, R. G., He, J., Jin, Y.
Conference Name2017 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)
Keywordscomposability, formal verification, Foundries, Hardware, Hardware design languages, hardware runtime verification, high-level security assurance, integrated circuits, IP runtime security verification, malicious behavior detection, Mathematical model, Metrics, Microelectronics Security, PCH framework, post-silicon stage, pre-silicon stage, proof-carrying hardware framework, pubcrawl, resilience, Resiliency, Runtime, runtime formal verification framework, SAT solving methods, security, security of data, symbolic execution, Trusted Computing, untrusted IPs, untrusted third-party vendors
Abstract

Untrusted third-party vendors and manufacturers have raised security concerns in hardware supply chain. Among all existing solutions, formal verification methods provide powerful solutions in detection malicious behaviors at the pre-silicon stage. However, little work have been done towards built-in hardware runtime verification at the post-silicon stage. In this paper, a runtime formal verification framework is proposed to evaluate the trust of hardware during its execution. This framework combines the symbolic execution and SAT solving methods to validate the user defined properties. The proposed framework has been demonstrated on an FPGA platform using an SoC design with untrusted IPs. The experimentation results show that the proposed approach can provide high-level security assurance for hardware at runtime.

URLhttps://ieeexplore.ieee.org/document/8353999/
DOI10.1109/AsianHOST.2017.8353999
Citation Keyguo_pch_2017