Visible to the public Hardening AES Hardware Implementations Against Fault and Error Inject Attacks

TitleHardening AES Hardware Implementations Against Fault and Error Inject Attacks
Publication TypeConference Paper
Year of Publication2018
AuthorsBu, Lake, Kinsy, Michel A.
Conference NameProceedings of the 2018 on Great Lakes Symposium on VLSI
PublisherACM
ISBN Number978-1-4503-5724-1
KeywordsAES, error correction, error detection, human factors, Metrics, non-linearity, pubcrawl, robust codes, Scalability, Tamper resistance
AbstractThe Advanced Encryption Standard (AES) enables secure transmission of confidential messages. Since its invention, there have been many proposed attacks against the scheme. For example, one can inject errors or faults to acquire the encryption keys. It has been shown that the AES algorithm itself does not provide a protection against these types of attacks. Therefore, additional techniques like error control codes (ECCs) have been proposed to detect active attacks. However, not all the proposed solutions show the adequate efficacy. For instance, linear ECCs have some critical limitations, especially when the injected errors are beyond their fault detection or tolerance capabilities. In this paper, we propose a new method based on a non-linear code to protect all four internal stages of the AES hardware implementation. With this method, the protected AES system is able to (a) detect all multiplicity of errors with a high probability and (b) correct them if the errors follow certain patterns or frequencies. Results shows that the proposed method provides much higher security and reliability to the AES hardware implementation with minimal overhead.
DOI10.1145/3194554.3194649
Citation Keybu_hardening_2018