Visible to the public A Machine Learning Attacks Resistant Two Stage Physical Unclonable Functions Design

TitleA Machine Learning Attacks Resistant Two Stage Physical Unclonable Functions Design
Publication TypeConference Paper
Year of Publication2018
AuthorsSu, H., Zwolinski, M., Halak, B.
Conference Name2018 IEEE 3rd International Verification and Security Workshop (IVSW)
ISBN Number978-1-5386-6544-2
Keywords32-bit current mirror, 65nm CMOS technology, Arbiter-PUF, asynchronous circuits, CMOS integrated circuits, composability, cryptography, Current Mirror PUF, enhancing security, Hash functions, learning (artificial intelligence), lightweight electronics, machine learning, machine learning attacks, Mathematical model, mirrors, modelling attacks, physical unclonable function (PUF), privacy, pubcrawl, PUF, reliability, resilience, Resiliency, security, security applications, security of data, stage physical unclonable functions design, traditional approaches, Transistors

Physical Unclonable Functions (PUFs) have been designed for many security applications such as identification, authentication of devices and key generation, especially for lightweight electronics. Traditional approaches to enhancing security, such as hash functions, may be expensive and resource dependent. However, modelling attacks using machine learning (ML) show the vulnerability of most PUFs. In this paper, a combination of a 32-bit current mirror and 16-bit arbiter PUFs in 65nm CMOS technology is proposed to improve resilience against modelling attacks. Both PUFs are vulnerable to machine learning attacks and we reduce the output prediction rate from 99.2% and 98.8% individually, to 60%.

Citation Keysu_machine_2018