Visible to the public Hardware Implementation of Dynamic Key Value Based Stream Cipher Using Chaotic Logistic Map

TitleHardware Implementation of Dynamic Key Value Based Stream Cipher Using Chaotic Logistic Map
Publication TypeConference Paper
Year of Publication2018
AuthorsTripathi, S. K., Pandian, K. K. S., Gupta, B.
Conference Name2018 2nd International Conference on Trends in Electronics and Informatics (ICOEI)
Date Publishedmay
ISBN Number978-1-5386-3570-4
Keywordsasymmetric key chaos based cryptography, binary sequence, binary sequences, chaos, Chaos based cryptography, chaotic logistic map, Ciphers, dynamic key value based stream cipher, Embedded systems, field programmable gate arrays, Field programmable gated array, FPGA device, frequency 62.2 MHz, Hardware, hardware security, hardware-based embedded system, Human Behavior, key scheduling, key stream, logistic map, Logistics, Metrics, NIST statistical, nonrecursive key, private key cryptography, PRNG, pseudorandom number generation, pseudorandom sequence generation, pubcrawl, public key cryptography, random key generation, random number generation, Random sequences, randomness tests, resilience, Resiliency, Scalability, stream cipher, symmetric key chaos based cryptography, Thermal analysis, Verilog HDL, X-power, Xilinx device
Abstract

In the last few decades, the relative simplicity of the logistic map made it a widely accepted point in the consideration of chaos, which is having the good properties of unpredictability, sensitiveness in the key values and ergodicity. Further, the system parameters fit the requirements of a cipher widely used in the field of cryptography, asymmetric and symmetric key chaos based cryptography, and for pseudorandom sequence generation. Also, the hardware-based embedded system is configured on FPGA devices for high performance. In this paper, a novel stream cipher using chaotic logistic map is proposed. The two chaotic logistic maps are coded using Verilog HDL and implemented on commercially available FPGA hardware using Xilinx device: XC3S250E for the part: FT256 and operated at frequency of 62.20 MHz to generate the non-recursive key which is used in key scheduling of pseudorandom number generation (PRNG) to produce the key stream. The realization of proposed cryptosystem in this FPGA device accomplishes the improved efficiency equal to 0.1186 Mbps/slice. Further, the generated binary sequence from the experiment is analyzed for X-power, thermal analysis, and randomness tests are performed using NIST statistical.

URLhttps://ieeexplore.ieee.org/document/8553914
DOI10.1109/ICOEI.2018.8553914
Citation Keytripathi_hardware_2018