Visible to the public Design of Generic Verification Procedure for IIC Protocol in UVM

TitleDesign of Generic Verification Procedure for IIC Protocol in UVM
Publication TypeConference Paper
Year of Publication2019
AuthorsE.V., Jaideep Varier, V., Prabakar, Balamurugan, Karthigha
Conference Name2019 3rd International Conference on Electronics, Communication and Aerospace Technology (ICECA)
ISBN Number978-1-7281-0167-5
KeywordsAerospace electronics, APB(Advanced peripheral bus), bugs, Clocks, code coverage, Collaboration, composability, compositionality, Conferences, DUT(Design under test), field buses, functional coverage, generic verification procedure, hardware description languages, Hardware design languages, IIC bus protocol, IIC controller, IIC protocol, Libraries, Mentor graphic Questasim 10.4e, Monitoring, policy-based governance, privacy, product development, program verification, protocol verification, Protocols, pubcrawl, SCL(Serial clock line), SDA(Serial data line), standard method, Synchronization, Universal Verification Methodology, UVC(Universal verification component), UVM, UVM(Univeral verification methodology), Verilog, Vivado

With the growth of technology, designs became more complex and may contain bugs. This makes verification an indispensable part in product development. UVM describe a standard method for verification of designs which is reusable and portable. This paper verifies IIC bus protocol using Universal Verification Methodology. IIC controller is designed in Verilog using Vivado. It have APB interface and its function and code coverage is carried out in Mentor graphic Questasim 10.4e. This work achieved 83.87% code coverage and 91.11% functional coverage.

Citation Keye.v._design_2019