Visible to the public Architecture Analysis and Verification of I3C Protocol

TitleArchitecture Analysis and Verification of I3C Protocol
Publication TypeConference Paper
Year of Publication2019
AuthorsMahale, Anusha, B.S., Kariyappa
Conference Name2019 3rd International Conference on Electronics, Communication and Aerospace Technology (ICECA)
Date Publishedjun
ISBN Number978-1-7281-0167-5
KeywordsAerospace electronics, back end design, base class library, Clocks, Collaboration, composability, compositionality, Conferences, digital integrated circuits, formal verification, front end design, hardware description languages, I3C, I3C bus protocol, improved inter integrated circuit, integrated circuit design, integrated circuit testing, IP networks, MIPI, Monitoring, Pins, policy-based governance, privacy, protocol verification, Protocols, pubcrawl, SoC, system Verilog, test environments, Universal Verification Methodology, UVM, verification components, verification environment, VLSI

In VLSI industry the design cycle is categorized into Front End Design and Back End Design. Front End Design flow is from Specifications to functional verification of RTL design. Back End Design is from logic synthesis to fabrication of chip. Handheld devices like Mobile SOC's is an amalgamation of many components like GPU, camera, sensor, display etc. on one single chip. In order to integrate these components protocols are needed. One such protocol in the emerging trend is I3C protocol. I3C is abbreviated as Improved Inter Integrated Circuit developed by Mobile Industry Processor Interface (MIPI) alliance. Most probably used for the interconnection of sensors in Mobile SOC's. The main motivation of adapting the standard is for the increase speed and low pin count in most of the hardware chips. The bus protocol is backward compatible with I2C devices. The paper includes detailed study I3C bus protocol and developing verification environment for the protocol. The test bench environment is written and verified using system Verilog and UVM. The Universal Verification Methodology (UVM) is base class library built using System Verilog which provides the fundamental blocks needed to quickly develop reusable and well-constructed verification components and test environments. The Functional Coverage of around 93.55 % and Code Coverage of around 98.89 % is achieved by verification closure.

Citation Keymahale_architecture_2019