Visible to the public Optimizing Quantum Circuits for Modular Exponentiation

TitleOptimizing Quantum Circuits for Modular Exponentiation
Publication TypeConference Paper
Year of Publication2019
AuthorsDas, Rakesh, Chattopadhyay, Anupam, Rahaman, Hafizur
Conference Name2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)
KeywordsComputer architecture, error correction, exponentiation, exponentiation functions, hardware description languages, Hardware design languages, Linear Nearest Neighbor (LNN), linear nearest neighbor property, logic circuits, logic design, logic designs, Logic gates, modular exponentiation, modular exponentiation functions, pubcrawl, Quantum Algorithm(QA), quantum architectures, quantum circuits, quantum computers, quantum computing, Quantum Error Correcting Codes (QECC), Quantum error correction, Qubit, Resiliency, reversible modular exponentiation function, Scalability, scalable synthesis methods, Tools, verilog implementation

Today's rapid progress in the physical implementation of quantum computers demands scalable synthesis methods to map practical logic designs to quantum architectures. There exist many quantum algorithms which use classical functions with superposition of states. Motivated by recent trends, in this paper, we show the design of quantum circuit to perform modular exponentiation functions using two different approaches. In the design phase, first we generate quantum circuit from a verilog implementation of exponentiation functions using synthesis tools and then apply two different Quantum Error Correction techniques. Finally the circuit is further optimized using the Linear Nearest Neighbor (LNN) Property. We demonstrate the effectiveness of our approach by generating a set of networks for the reversible modular exponentiation function for a set of input values. At the end of the work, we have summarized the obtained results, where a cost analysis over our developed approaches has been made. Experimental results show that depending on the choice of different QECC methods the performance figures can vary by up to 11%, 10%, 8% in T-count, number of qubits, number of gates respectively.

Citation Keydas_optimizing_2019