Visible to the public Statistical Power Analysis for IoT Device Oriented Encryption with Glitch Canceller

TitleStatistical Power Analysis for IoT Device Oriented Encryption with Glitch Canceller
Publication TypeConference Paper
Year of Publication2019
AuthorsTakemoto, Shu, Nozaki, Yusuke, Yoshikawa, Masaya
Conference Name2019 IEEE 11th International Workshop on Computational Intelligence and Applications (IWCIA)
ISBN Number978-1-7281-2429-2
KeywordsBig Data, cryptography, field programmable gate arrays, field-programmable gate array, glitch canceller, hardware security, Human Behavior, human factors, Internet of Things, IoT device oriented encryption, IoT devise, low-power, lowest latency cryptography, Metrics, power consumption, PRINCE, privacy, pubcrawl, Scalability, Side-channel attack, statistical analysis, statistical power analysis, Tamper resistance

Big data which is collected by IoT devices is utilized in various businesses. For security and privacy, some data must be encrypted. IoT devices for encryption require not only to tamper resistance but also low latency and low power. PRINCE is one of the lowest latency cryptography. A glitch canceller reduces power consumption, although it affects tamper resistance. Therefore, this study evaluates the tamper resistance of dedicated hardware with glitch canceller for PRINCE by statistical power analysis and T-test. The evaluation experiments in this study performed on field-programmable gate array (FPGA), and the results revealed the vulnerability of dedicated hardware implementation with glitch canceller.

Citation Keytakemoto_statistical_2019