Visible to the public Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices

TitleNetworks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices
Publication TypeConference Paper
Year of Publication2019
AuthorsAscia, Giuseppe, Catania, Vincenzo, Monteleone, Salvatore, Palesi, Maurizio, Patti, Davide, Jose, John
Conference Name2019 Sixth International Conference on Internet of Things: Systems, Management and Security (IOTSMS)
Date Publishedoct
KeywordsArtificial neural networks, circuit optimisation, Deep Neural Network accelerator, deep neural network inferences, Design Space Exploration, Energy analysis, integrated circuit design, Internet of Things, IoT edge devices, low-power electronics, massive parallel cores, Measurement, Memory management, memory size, Metrics, network on chip security, network routing, network-on-chip, neural chips, Neurons, NoC-based deep neural network accelerators, on-chip communication, performance evaluation, resilience, Resiliency, resource-constrained embedded devices, Scalability, Space exploration, system-on-chip
AbstractThe need for performing deep neural network inferences on resource-constrained embedded devices (e.g., Internet of Things nodes) requires specialized architectures to achieve the best trade-off among performance, energy, and cost. One of the most promising architectures in this context is based on massive parallel and specialized cores interconnected by means of a Network-on-Chip (NoC). In this paper, we extensively evaluate NoC-based deep neural network accelerators by exploring the design space spanned by several architectural parameters including, network size, routing algorithm, local memory size, link width, and number of memory interfaces. We show how latency is mainly dominated by the on-chip communication whereas energy consumption is mainly accounted by memory (both on-chip and off-chip). The outcome of the analysis, thus, pushes toward a research line devoted to the optimization of the on-chip communication fabric and the memory subsystem for performance improvement and energy efficiency, respectively.
Citation Keyascia_networks–chip_2019