Visible to the public Deep Packet Inspection Through Virtual Platforms using System-On-Chip FPGAs

TitleDeep Packet Inspection Through Virtual Platforms using System-On-Chip FPGAs
Publication TypeConference Paper
Year of Publication2019
AuthorsLeón, Raquel, Domínguez, Adrián, Carballo, Pedro P., Núñez, Antonio
Conference Name2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS)
ISBN Number978-1-7281-5458-9
KeywordsComputer architecture, CPU-DMA based architecture, deep packet inspection, ESL, field programmable gate arrays, Hardware, hardware accelerators, hardware-IP based architecture, hybrid CPU/FPGA, Inspection, logic design, Mentor Vista, pubcrawl, resilience, Resiliency, Scalability, search engines, Software, system on chip, system-on-chip, system-on-chip FPGA, time-domain analysis, time-varying systems, TLM, transaction level modeling, virtual platform, virtual platforms

Virtual platforms provide a full hardware/software platform to study device limitations in an early stages of the design flow and to develop software without requiring a physical implementation. This paper describes the development process of a virtual platform for Deep Packet Inspection (DPI) hardware accelerators by using Transaction Level Modeling (TLM). We propose two DPI architectures oriented to System-on-Chip FPGA. The first architecture, CPU-DMA based architecture, is a hybrid CPU/FPGA where the packets are filtered in the software domain. The second architecture, Hardware-IP based architecture, is mainly implemented in the hardware domain. We have created two virtual platforms and performed the simulation, the debugging and the analysis of the hardware/software features, in order to compare results for both architectures.

Citation Keyleon_deep_2019