Visible to the public FPGA Implementation of Internet Key Exchange Based on Chaotic Cryptosystem

TitleFPGA Implementation of Internet Key Exchange Based on Chaotic Cryptosystem
Publication TypeConference Paper
Year of Publication2019
AuthorsBouteghrine, Belqassim, Rabiai, Mohammed, Tanougast, Camel, Sadoudi, Said
Conference Name2019 10th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS)
Keywords4-dimension chaotic system, chaotic communication, chaotic cryptography, chaotic cryptosystem, chaotic cryptosystem solution, composability, computer network security, cryptographic protocols, cryptography, data phase transfer, DH-HEMTs, field programmable gate arrays, FPGA, FPGA implementation, IKE, IKE protocol, Internet, Internet key exchange protocol, IPsec, IPSec protocol, keys phase exchange, man in the middle attack, network communication domain, network protocol, Predictive Metrics, Protocols, pubcrawl, Resiliency, SA, securing communications, security association attack, Synchronization, word length 128 bit
AbstractIn network communication domain, one of the most widely used protocol for encrypting data and securing communications is the IPSec protocol. The design of this protocol is based on two main phases which are: exchanging keys phase and transferring data phase. In this paper we focus on enhancing the exchanging keys phase which is included in the security association (SA), using a chaotic cryptosystem. Initially IPSec is based on the Internet Key Exchange (IKE) protocol for establishing the SA. Actually IKE protocol is in charge for negotiating the connection and for authenticating both nodes. However; using IKE gives rise to a major problem related to security attack such as the Man in the Middle Attack. In this paper, we propose a chaotic cryptosystem solution to generate SA file for the connected nodes of the network. By solving a 4-Dimension chaotic system, a SA file that includes 128-bit keys will be established. The proposed solution is implemented and tested using FPGA boards.
Citation Keybouteghrine_fpga_2019