Visible to the public Hardware Steganography for IP Core Protection of Fault Secured DSP Cores

TitleHardware Steganography for IP Core Protection of Fault Secured DSP Cores
Publication TypeConference Paper
Year of Publication2019
AuthorsSengupta, A., Gupta, G., Jalan, H.
Conference Name2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin)
Keywordscolored interval graph, composability, digital signal processing chips, digital signatures, DSP, DSP based IP cores, encoding rule, Entropy, entropy thresholding, entropy value, Fault secure, fault secured DSP cores, graph theory, hardware steganography, high level synthesis, industrial property, IP core, IP core protection, IP piracy, logic design, multimedia cores, policy-based governance, pubcrawl, Resiliency, signature free approach, signature size, steganography, transient fault secured IP cores, vendor defined signature, Watermarking
AbstractSecurity of transient fault secured IP cores against piracy, false claim of ownership can be achieved during high level synthesis, especially when handling DSP or multimedia cores. Though watermarking that involves implanting a vendor defined signature onto the design can be useful, however research has shown its limitations such as less designer control, high overhead due to extreme dependency on signature size, combination and encoding rule. This paper proposes an alternative paradigm called `hardware steganography' where hidden additional designer's constraints are implanted in a fault secured IP core using entropy thresholding. In proposed hardware steganography, concealed information in the form of additional edges having a specific entropy value is embedded in the colored interval graph (CIG). This is a signature free approach and ensures high designer control (more robustness and stronger proof of authorship) as well as lower overhead than watermarking schemes used for DSP based IP cores.
Citation Keysengupta_hardware_2019