Visible to the public Physical Unclonable Functions (PUFs) Entangled Trusted Computing Base

TitlePhysical Unclonable Functions (PUFs) Entangled Trusted Computing Base
Publication TypeConference Paper
Year of Publication2019
AuthorsHamadeh, H., Tyagi, A.
Conference Name2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)
KeywordsClocks, composability, copy protection, cyber-physical system security, data-dependent delay, delays, digital signatures, field programmable gate arrays, logic circuits, logic design, microprocessor chips, neural style transfer, particular program instruction, physical unclonable functions, Pollution measurement, Predictive Metrics, processor chip ALU silicon biometrics, program execution, pubcrawl, reliability, Resiliency, Scalability, Semiconductor device measurement, Software, software instruction, Software measurement, software measurement physical unclonable function, SW-PUF measurements, Trusted Computing, trusted computing base, trusted platform modules
AbstractThe center-piece of this work is a software measurement physical unclonable function (PUF). It measures processor chip ALU silicon biometrics in a manner similar to all PUFs. Additionally, it composes the silicon measurement with the data-dependent delay of a particular program instruction in a way that is difficult to decompose through a mathematical model. This approach ensures that each software instruction is measured if computed. The SW-PUF measurements bind the execution of software to a specific processor with a corresponding certificate. This makes the SW-PUF a promising candidate for applications requiring Trusted Computing. For instance, it could measure the integrity of an execution path by generating a signature that is unique to the specific program execution path and the processor chip. We present an area and energy-efficient scheme based on the SW-PUF to provide a more robust root of trust for measurement than the existing trusted platform module (TPM). To explore the feasibility of the proposed design, the SW-PUF has been implemented in HSPICE using 45 nm technology and evaluated on the FPGA platform.
Citation Keyhamadeh_physical_2019