Visible to the public SRACARE: Secure Remote Attestation with Code Authentication and Resilience Engine

TitleSRACARE: Secure Remote Attestation with Code Authentication and Resilience Engine
Publication TypeConference Paper
Year of Publication2020
AuthorsDave, Avani, Banerjee, Nilanjan, Patel, Chintan
Conference Name2020 IEEE International Conference on Embedded Software and Systems (ICESS)
Date PublishedDec. 2020
ISBN Number978-1-7281-6466-3
Keywordsattack resilience, attestation, composability, Computer architecture, embedded system architecture, Fault Tolerant and Trusted Embedded Systems, Human Behavior, Intelligent Embedded Systems, IoT devices, Malware, performance evaluation, Protocols, Prototypes, pubcrawl, remote attestation, resilience, Resiliency, Secure-boot, Software

Recent technological advancements have enabled proliferated use of small embedded and IoT devices for collecting, processing, and transferring the security-critical information and user data. This exponential use has acted as a catalyst in the recent growth of sophisticated attacks such as the replay, man-in-the-middle, and malicious code modification to slink, leak, tweak or exploit the security-critical information in malevolent activities. Therefore, secure communication and software state assurance (at run-time and boot-time) of the device has emerged as open security problems. Furthermore, these devices need to have an appropriate recovery mechanism to bring them back to the known-good operational state. Previous researchers have demonstrated independent methods for attack detection and safeguard. However, the majority of them lack in providing onboard system recovery and secure communication techniques. To bridge this gap, this manuscript proposes SRACARE - a framework that utilizes the custom lightweight, secure communication protocol that performs remote/local attestation, and secure boot with an onboard resilience recovery mechanism to protect the devices from the above-mentioned attacks. The prototype employs an efficient lightweight, low-power 32-bit RISC-V processor, secure communication protocol, code authentication, and resilience engine running on the Artix 7 Field Programmable Gate Array (FPGA) board. This work presents the performance evaluation and state-of-the-art comparison results, which shows promising resilience to attacks and demonstrate the novel protection mechanism with onboard recovery. The framework achieves these with only 8% performance overhead and a very small increase in hardware-software footprint.

Citation Keydave_sracare_2020