Visible to the public A HES for Low Speed Processors

TitleA HES for Low Speed Processors
Publication TypeConference Paper
Year of Publication2020
AuthorsChibaya, Colin, Jowa, Viola Jubile, Rupere, Taurayi
Conference Name2020 2nd International Multidisciplinary Information Technology and Engineering Conference (IMITEC)
Date Publishednov
KeywordsCiphers, composability, decryption, DES, Encryption, HES, Memory management, Metrics, Program processors, pubcrawl, resilience, Resiliency, Robustness, security mechanisms, security services, Standards, Task Analysis, white box cryptography
AbstractAdaptation of e-commerce in third world countries requires more secure computing facilities. Online data is vulnerable and susceptible to active attacks. Hundreds of security mechanisms and services have been proposed to curb this challenge. However, available security mechanisms, sufficiently strong, are heavy for the machines used. To secure online data where machines' processing power and memory are deficient, a Hybrid Encryption Standard (HES) is proposed. The HES is built on the Data Encryption Standard (DES) algorithm and its siblings. The component units of the DES are redesigned towards reduced demands for processing power and memory. Precisely, white box designs of IP tables, PC tables, Expansion tables, Rotation tables, S-boxes and P-boxes are proposed, all aimed at reducing the processing time and memory demands. Evaluation of the performance of the HES algorithm against the performance of the traditional DES algorithm reveal that the HES out-performs the DES with regards to speed, memory demands, and general acceptance by novice practitioners in the cryptography field. In addition, reproducibility and flexibility are attractive features of the HES over the DES.
Citation Keychibaya_hes_2020