OutputSignalPort (Atom)

Ancestors

• Feature
• Port
• SignalPortType
• SignalPort
• OutputSignalPort

Represents an output signal interface to a component, test component, or component assembly.

• BehaviorModelsAspect: ComponentType, FaultModeModel, ModelicaAggregateInterface, ModelicaModelType, SignalFlowModel
• All: AggregatePort, DesignContainer, DesignElement, TestBench, TestBenchType, Workflow
• TBDriverMonitorAspect: TestBench
• TBRequirementsAspect: TestBench

• Parents: AggregatePort, Component, ComponentAssembly, ComponentType, DesignContainer, DesignElement, TestComponent

• From node: InformationFlow, Signal2Metric, SignalPort2PPInput, MapToVTC_Signal
• To node: InformationFlow, SignalDriverMap, SignalPortMap

• Structural Semantics: CyPhyML.4ml
• Annotated Specification: CyPhyComponentInterconnectionsExplained.4ml, ModelicaMappingExplained.4ml