Skip to Main Content Area
CPS-VO
Contact Support
Browse
Calendar
Announcements
Repositories
Groups
Search
Search for Content
Search for a Group
Search for People
Search for a Project
Tagcloud
› Go to login screen
Not a member?
Click here to register!
Forgot username or password?
Cyber-Physical Systems Virtual Organization
Fostering collaboration among CPS professionals in academia, government, and industry
CPS-VO
UVM
biblio
Architecture Analysis and Verification of I3C Protocol
Submitted by
grigby1
on Tue, 11/12/2019 - 4:29pm
Aerospace electronics
back end design
base class library
Clocks
collaboration
composability
Compositionality
Conferences
digital integrated circuits
formal verification
front end design
hardware description languages
I3C
I3C bus protocol
improved inter integrated circuit
integrated circuit design
integrated circuit testing
IP networks
MIPI
Monitoring
Pins
policy-based governance
privacy
protocol verification
Protocols
pubcrawl
SoC
system Verilog
test environments
Universal Verification Methodology
UVM
verification components
verification environment
VLSI
biblio
Design of Generic Verification Procedure for IIC Protocol in UVM
Submitted by
grigby1
on Tue, 11/12/2019 - 4:29pm
Aerospace electronics
APB(Advanced peripheral bus)
bugs
Clocks
code coverage
collaboration
composability
Compositionality
Conferences
DUT(Design under test)
field buses
functional coverage
generic verification procedure
hardware description languages
Hardware design languages
IIC bus protocol
IIC controller
IIC protocol
Libraries
Mentor graphic Questasim 10.4e
Monitoring
policy-based governance
privacy
product development
program verification
protocol verification
Protocols
pubcrawl
SCL(Serial clock line)
SDA(Serial data line)
standard method
Synchronization
Universal Verification Methodology
UVC(Universal verification component)
UVM
UVM(Univeral verification methodology)
Verilog
Vivado
biblio
Robust Functional Verification Framework Based in UVM Applied to an AES Encryption Module
Submitted by
grigby1
on Fri, 06/28/2019 - 10:36am
AES encryption module
Compositionality
Cryptography
design requirements
digital design industry
direct verification methodologies
encryption
formal verification
functional verification
hardware description languages
high-level designs
Industries
information-security applications
Measurement
Metrics
pubcrawl
Reliability engineering
resilience
Resiliency
robust functional verification framework
Scalability
scalable verification
standards
System Verilog-based functional verification
Universal Verification Methodology
UVM
Verification Framework
biblio
A Scalable and Reconfigurable Verification and Benchmark Environment for Network on Chip Architecture
Submitted by
grigby1
on Wed, 05/09/2018 - 2:47pm
benchmark
benchmark environment
Benchmark testing
complex on-chip communication problems
Compositionality
Generators
integrated circuit design
interconnection architectures
Metrics
Monitoring
network-on-chip
network-on-chip architecture
NoC
Object oriented modeling
on-chip component
pubcrawl
reconfigurable verification
resilience
Resiliency
reusable methodology
Scalability
scalable verification
standardized methodology
system-on-chip
Throughput
traffic control
Universal Verification Methodology
UVM
verification
