MES 2014
Date: Jun 14, 2014 8:00 am – Jun 18, 2014 5:00 pm
Location: Minneapolis, MN
Second ACM International Workshop on Manycore Embedded Systems (MES)
in conjunction with the 41st International symposium on Computer Architecture (ISCA-2014)
General Scope
Many-core embedded systems (MES) are moving towards the integration of hundreds of cores on a single chip and hold the promise of increasing performance through parallelism. As the number of cores integrated into a chip increases, the on-chip communication becomes a power and performance bottleneck in future MESs. Networks-on-Chip (NoC) have has been proposed as the most viable solution to meet the performance and design productivity requirements of the complex on-chip communication infrastructure. NoCs provide an infrastructure for better modularity, scalability, fault-tolerance, and higher bandwidth compared to traditional infrastructures. On the other hand, developing applications using the full power of NoC-based MES requires software developers to transition from writing serial programs to writing parallel programs. On top of that, contemporary Operating Systems (OS) have been designed to run on a small number of reliable cores and are not able to scale up to hundreds of cores. Therefore, designing scalable and fault-tolerant OSs will be a tremendous challenge in future MESs.
In addition, as neuromorphic and mixed-signal architectures are emerging as an alternative solution beyond the conventional digital von Neumann machines for complex applications, we would like to highlight such emerging architectures in this workshop.
The goal of this workshop is to bring together the researchers from academia and the experts from industry to present and discuss innovative ideas and solutions in the design, modeling, prototyping, programming, and implementation of MES. Topics of interest include, but are not limited to:
- Networks-on-Chip
- Brain-inspired Computing Architectures
- Mapping of applications
- (Embedded) OS
- 3D Stacked Architectures
- Reliability issues
- Physical design
- Synthesis, verification, debug & test
- Performance and power issues
- Reconfigurability aspects
- FPGA implementation
- Prallel programming model and scalable software
- Compiler technologies
- Many-core as accelerators
- Heterogeneity challenges
- Data-centers
- Dynamic power management and energy harvesting
Submissions from EU projects in progress as well as seminal work in the field are also encouraged. Submissions should not exceed 8 pages, including tables and figures, and must be formatted in accordance to the ACM two column style. Submission of a paper should be regarded as an undertaking whereby, should the paper be accepted, at least one of the authors will register for the conference and present the work.
Proceeding and Special Issue:
The accepted papers will be published in the ACM Digital Library (pending).
Selected papers will be considered to appear in a special issue of Elsevier's Journal of Systems Architecture (JSA).
Instruction for Paper Submissions:
You are invited to submit original and unpublished research works on topics related to many-core embedded systems. Submitted papers must not have been published or simultaneously submitted elsewhere. Please submit a PDF copy of your full manuscript, not to exceed 8 double-column ACM formatted pages, and include up to 6 keywords and an abstract of no more than 400 words. Papers must be formatted in accordance to the ACM two column style. ACM Word or LaTeX style templates are available here. In addition, Authors should apply ACM Computing Classification categories and terms.
Submit a PDF copy of your full manuscript to the Workshop EasyChair link at:
https://www.easychair.org/conferences/?conf=mes2014
Organizers:
Masoud Daneshtalab, University of Turku, Finland
Maurizio Palesi, Kore University, Italy
Federico Angiolini, iNoCs, Switzerland
Program Chairs:
Juha Plosila, University of Turku, Finland
Masoumeh Ebrahimi, KTH Royal Institute of Technology, Sweden
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Second ACM International Workshop on Manycore Embedded Systems (MES)
in conjunction with the 41st International symposium on Computer Architecture (ISCA-2014)
General Scope
Many-core embedded systems (MES) are moving towards the integration of hundreds of cores on a single chip and hold the promise of increasing performance through parallelism. As the number of cores integrated into a chip increases, the on-chip communication becomes a power and performance bottleneck in future MESs. Networks-on-Chip (NoC) have has been proposed as the most viable solution to meet the performance and design productivity requirements of the complex on-chip communication infrastructure. NoCs provide an infrastructure for better modularity, scalability, fault-tolerance, and higher bandwidth compared to traditional infrastructures. On the other hand, developing applications using the full power of NoC-based MES requires software developers to transition from writing serial programs to writing parallel programs. On top of that, contemporary Operating Systems (OS) have been designed to run on a small number of reliable cores and are not able to scale up to hundreds of cores. Therefore, designing scalable and fault-tolerant OSs will be a tremendous challenge in future MESs.
In addition, as neuromorphic and mixed-signal architectures are emerging as an alternative solution beyond the conventional digital von Neumann machines for complex applications, we would like to highlight such emerging architectures in this workshop.
The goal of this workshop is to bring together the researchers from academia and the experts from industry to present and discuss innovative ideas and solutions in the design, modeling, prototyping, programming, and implementation of MES. Topics of interest include, but are not limited to:
- Networks-on-Chip
- Brain-inspired Computing Architectures
- Mapping of applications
- (Embedded) OS
- 3D Stacked Architectures
- Reliability issues
- Physical design
- Synthesis, verification, debug & test
- Performance and power issues
- Reconfigurability aspects
- FPGA implementation
- Prallel programming model and scalable software
- Compiler technologies
- Many-core as accelerators
- Heterogeneity challenges
- Data-centers
- Dynamic power management and energy harvesting
Submissions from EU projects in progress as well as seminal work in the field are also encouraged. Submissions should not exceed 8 pages, including tables and figures, and must be formatted in accordance to the ACM two column style. Submission of a paper should be regarded as an undertaking whereby, should the paper be accepted, at least one of the authors will register for the conference and present the work.
Proceeding and Special Issue:
The accepted papers will be published in the ACM Digital Library (pending).
Selected papers will be considered to appear in a special issue of Elsevier's Journal of Systems Architecture (JSA).
Instruction for Paper Submissions:
You are invited to submit original and unpublished research works on topics related to many-core embedded systems. Submitted papers must not have been published or simultaneously submitted elsewhere. Please submit a PDF copy of your full manuscript, not to exceed 8 double-column ACM formatted pages, and include up to 6 keywords and an abstract of no more than 400 words. Papers must be formatted in accordance to the ACM two column style. ACM Word or LaTeX style templates are available here. In addition, Authors should apply ACM Computing Classification categories and terms.
Submit a PDF copy of your full manuscript to the Workshop EasyChair link at:
https://www.easychair.org/conferences/?conf=mes2014
Organizers:
Masoud Daneshtalab, University of Turku, Finland
Maurizio Palesi, Kore University, Italy
Federico Angiolini, iNoCs, Switzerland
Program Chairs:
Juha Plosila, University of Turku, Finland
Masoumeh Ebrahimi, KTH Royal Institute of Technology, Sweden