HiRES 2016
Date: Jan 19, 2016 1:00 am – Jan 19, 2016 10:00 am
Location: Prague, Czech Republic
Call for Papers
4th Workshop on High-performance and Real-Time Embedded Systems (HiRES 2016)
To be held in conjunction with the 11th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC 2016)
Goal of the Workshop
Increasingly, time is a relevant concern which impacts in all application areas and challenges ahead. Real-time requirements can be found in applications ranging from large-scale data processing systems to deeply embedded devices. Examples include safety-critical systems with high-performance requirements, such as collision avoidance and autonomous driving in avionics and automotive respectively, in which the correct timing behaviour is of paramount importance; consumer systems, such as video processing in TV sets and games; or real-time complex event processing applications, such as online trading or real-time traffic management.
In all these applications, systems are expected to cope with an increasing demand of functional and non-functional requirements, with the corresponding increase in processing capabilities, paving the way for high-performance architectures, of which multi-core and many-core systems are becoming pervasive. The capabilities and challenges of parallelization as a means to provide higher performance is a cross-cutting concern.
This workshop intends to bring together researchers and engineers in the confluence of high-performance, embedded systems and real-time systems. The goal is to allow for fruitful discussions on the challenges and research directions that should be tackled by the community.
This is the 4th workshop in the series. Information on previous workshop can be found at:
- HiRES 2013: http://www.cister.isep.ipp.pt/hires2013/
- HiRES 2014: http://www.cister.isep.ipp.pt/hires2014/
- HiRES 2015: http://www.cister.isep.ipp.pt/hires2015/
Topics of interest to this edition of the workshop include but are not limited to:
- Runtimes and operating systems combining high-performance and predictability requirements;
- Programming models and compiler support for providing real-time capabilities to multi- and many-core architectures;
- Models and tools for code generation, system verification and validation;
- Worst-case execution time analysis, parallel/dag-based task models, schedulability analysis of multi- and many-core systems;
- Heterogeneous multi-core embedded real-time architectures, many-core accelerators;
- Time-predictable multi- and many-core processor architectures;
- Time-aware energy-efficiency.
Important dates
- Abstract registration: October 14, 2015
- Paper submission: October 20, 2015
- Notification to authors: November 23, 2015
- Final version of accepted papers: December 15, 2015
- Workshop: January 19, 2016
Organizers
- Luís Miguel Pinho, CISTER, Portugal
- Eduardo Quiñones, BSC, Spain
- Sascha Uhrig, Airbus Group Innovations, Germany
Program Committee
- Albert Cohen, INRIA, France
- Alejandro Alonso, Universidad Politécnica de Madrid, Spain
- Andrea Marongiu, ETHZ, Switzerland
- Eduardo Quiñones, BSC, Spain
- Johan Eker, Ericsson, Sweden
- Luís Miguel Pinho, CISTER, Portugal
- Marko Bertogna, University of Modena, Italy
- Martin Schoeberl, DTU, Denmark
- Neil Audsley, University of York, UK
- Philippe Bonnot, Thales, France
- Sascha Uhrig, TU Dortmund, Germany
- Theo Ungerer, University of Augsburg, Germany
- Zlatko Petrov, Honeywell, Czech Republic
Submitted by Anonymous
on
Call for Papers
4th Workshop on High-performance and Real-Time Embedded Systems (HiRES 2016)
To be held in conjunction with the 11th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC 2016)
Goal of the Workshop
Increasingly, time is a relevant concern which impacts in all application areas and challenges ahead. Real-time requirements can be found in applications ranging from large-scale data processing systems to deeply embedded devices. Examples include safety-critical systems with high-performance requirements, such as collision avoidance and autonomous driving in avionics and automotive respectively, in which the correct timing behaviour is of paramount importance; consumer systems, such as video processing in TV sets and games; or real-time complex event processing applications, such as online trading or real-time traffic management.
In all these applications, systems are expected to cope with an increasing demand of functional and non-functional requirements, with the corresponding increase in processing capabilities, paving the way for high-performance architectures, of which multi-core and many-core systems are becoming pervasive. The capabilities and challenges of parallelization as a means to provide higher performance is a cross-cutting concern.
This workshop intends to bring together researchers and engineers in the confluence of high-performance, embedded systems and real-time systems. The goal is to allow for fruitful discussions on the challenges and research directions that should be tackled by the community.
This is the 4th workshop in the series. Information on previous workshop can be found at:
- HiRES 2013: http://www.cister.isep.ipp.pt/hires2013/
- HiRES 2014: http://www.cister.isep.ipp.pt/hires2014/
- HiRES 2015: http://www.cister.isep.ipp.pt/hires2015/
Topics of interest to this edition of the workshop include but are not limited to:
- Runtimes and operating systems combining high-performance and predictability requirements;
- Programming models and compiler support for providing real-time capabilities to multi- and many-core architectures;
- Models and tools for code generation, system verification and validation;
- Worst-case execution time analysis, parallel/dag-based task models, schedulability analysis of multi- and many-core systems;
- Heterogeneous multi-core embedded real-time architectures, many-core accelerators;
- Time-predictable multi- and many-core processor architectures;
- Time-aware energy-efficiency.
Important dates
- Abstract registration: October 14, 2015
- Paper submission: October 20, 2015
- Notification to authors: November 23, 2015
- Final version of accepted papers: December 15, 2015
- Workshop: January 19, 2016
Organizers
- Luís Miguel Pinho, CISTER, Portugal
- Eduardo Quiñones, BSC, Spain
- Sascha Uhrig, Airbus Group Innovations, Germany
Program Committee
- Albert Cohen, INRIA, France
- Alejandro Alonso, Universidad Politécnica de Madrid, Spain
- Andrea Marongiu, ETHZ, Switzerland
- Eduardo Quiñones, BSC, Spain
- Johan Eker, Ericsson, Sweden
- Luís Miguel Pinho, CISTER, Portugal
- Marko Bertogna, University of Modena, Italy
- Martin Schoeberl, DTU, Denmark
- Neil Audsley, University of York, UK
- Philippe Bonnot, Thales, France
- Sascha Uhrig, TU Dortmund, Germany
- Theo Ungerer, University of Augsburg, Germany
- Zlatko Petrov, Honeywell, Czech Republic