WRC2016
Date: Jan 19, 2016 12:00 am – Jan 19, 2016 11:00 am
Location: Prague, Czech Republic
10th HiPEAC Workshop on Reconfigurable Computing (WRC'2016)
The HiPEAC Workshop on Reconfigurable Computing (WRC) provides a forum for researchers active in domains within the reconfigurable computing area. Its main focus is on reconfigurable architectures, tools and algorithms that facilitate reconfigurable systems and applications tailored for reconfigurable platforms. The WRC’2016 forum intends to provide a substantially different event from the well-known conferences and workshops related to reconfigurable computing, by focusing on an informal way to discuss challenges, new ideas, future trends, and work in progress. For the second time, the Hot Topic of WRC is High Performance Reconfigurable Computing. We encourage submissions in the following areas:
- High Performance Reconfigurable Computing: languages and compilation, tools and design flows, adaptability, virtualization, reliability, and communication.
- Reconfigurable Architectures: novel reconfigurable fabrics, memory design, low power design, adaptive architectures, networks on chip, fault tolerance.
- Reconfigurable Tools and Technologies: system-level design, HW/SW co-design, partitioning, mapping, modeling, cost and power optimization, dynamic reconfiguration, verification, testing, benchmarking.
- Reconfigurable Applications and Algorithms: scientific computing, adaptive computing, bio-inspired computing, domain-specific computing, multimedia, bioinformatics, signal processing, rapid prototyping, low-latency.
- Big Data Architectures: Scalable reconfigurable architectures for graph, text, and multimedia data mining, machine learning, and deep neural networks.
- System Security: cryptographic hardware architectures, security processors, countermeasures against side-channel attacks, and secure cloud computing.
Selected papers will be invited for publication in a special issue of the Springer’s Journal of Signal Processing Systems (JSPS), dedicated to WRC’2016.
Quick Links
- Workshop: http://www.fe.up.pt/wrc2016
- Submissions: https://easychair.org/conferences/?conf=wrc2016
- HiPEAC 2016: https://www.hipeac.net/2016/prague/
Workshop Organization
General Co-Chair
Juergen Becker, KIT, Germany
e-mail: juergen.becker@kit.edu
General Co-Chair
João M. P. Cardoso, University of Porto, Portugal
e-mail: jmpc@acm.org
Program Co-Chair
Kubilay Atasu, IBM Research - Zurich, Switzerland
e-mail: kat@zurich.ibm.com
Program Co-Chair
Steven Derrien, IRISA/INRIA, University of Rennes 1, France
e-mail: steven.derrien@univ-rennes1.fr
Web Chair
João Bispo, University of Porto, Portugal
e-mail: jbispo@fe.up.pt
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10th HiPEAC Workshop on Reconfigurable Computing (WRC'2016)
The HiPEAC Workshop on Reconfigurable Computing (WRC) provides a forum for researchers active in domains within the reconfigurable computing area. Its main focus is on reconfigurable architectures, tools and algorithms that facilitate reconfigurable systems and applications tailored for reconfigurable platforms. The WRC’2016 forum intends to provide a substantially different event from the well-known conferences and workshops related to reconfigurable computing, by focusing on an informal way to discuss challenges, new ideas, future trends, and work in progress. For the second time, the Hot Topic of WRC is High Performance Reconfigurable Computing. We encourage submissions in the following areas:
- High Performance Reconfigurable Computing: languages and compilation, tools and design flows, adaptability, virtualization, reliability, and communication.
- Reconfigurable Architectures: novel reconfigurable fabrics, memory design, low power design, adaptive architectures, networks on chip, fault tolerance.
- Reconfigurable Tools and Technologies: system-level design, HW/SW co-design, partitioning, mapping, modeling, cost and power optimization, dynamic reconfiguration, verification, testing, benchmarking.
- Reconfigurable Applications and Algorithms: scientific computing, adaptive computing, bio-inspired computing, domain-specific computing, multimedia, bioinformatics, signal processing, rapid prototyping, low-latency.
- Big Data Architectures: Scalable reconfigurable architectures for graph, text, and multimedia data mining, machine learning, and deep neural networks.
- System Security: cryptographic hardware architectures, security processors, countermeasures against side-channel attacks, and secure cloud computing.
Selected papers will be invited for publication in a special issue of the Springer’s Journal of Signal Processing Systems (JSPS), dedicated to WRC’2016.
Quick Links
- Workshop: http://www.fe.up.pt/wrc2016
- Submissions: https://easychair.org/conferences/?conf=wrc2016
- HiPEAC 2016: https://www.hipeac.net/2016/prague/
Workshop Organization
General Co-Chair
Juergen Becker, KIT, Germany
e-mail: juergen.becker@kit.edu
General Co-Chair
João M. P. Cardoso, University of Porto, Portugal
e-mail: jmpc@acm.org
Program Co-Chair
Kubilay Atasu, IBM Research - Zurich, Switzerland
e-mail: kat@zurich.ibm.com
Program Co-Chair
Steven Derrien, IRISA/INRIA, University of Rennes 1, France
e-mail: steven.derrien@univ-rennes1.fr
Web Chair
João Bispo, University of Porto, Portugal
e-mail: jbispo@fe.up.pt