WCET 2016
Date: Jul 05, 2016 12:00 am – Jul 05, 2016 11:30 am
Location: Toulouse, France
16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)
Toulouse, France | 5th July 2016 | http://wcet2016.compute.dtu.dk
in conjunction with the Euromicro Conference on Real-Time Systems (ECRTS)
WCET 2016 is kindly supported by TACLe (www.tacle.eu), an European COST-Action on Timing Analysis on Code-Level.
GOALS AND TOPICS
A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori. Perhaps paradoxically, this problem has become more difficult by the introduction of performance-enhancing architectural elements, such as caches, pipelines, and multi-threading, which introduce a large degree of uncertainty and make timing guarantees harder to provide.
The WCET workshop focuses on the analysis and design of timing-predictable systems, with a strong emphasis on worst-case execution time (WCET) analysis.
Topics of interest include all aspects of timing analysis and timing-predictability. This includes (but is not limited to):
- WCET analysis for multi-threaded and multi-core systems
- Low-level timing analysis, modeling and analysis of processor features
- Flow analysis for WCET, loop bounds, infeasible paths
- Measurement-based WCET analysis
- Different approaches to WCET computation
- Probabilistic timing analysis
- Tools for WCET analysis
- Integration of WCET and schedulability analysis
- Integration of WCET analysis in development processes
- Strategies to reduce the complexity of WCET analysis
- Processor and hardware design for timing predictability
- Program design for timing predictability
- Compiler-based optimization of worst-case timing
- Timing-predictable, resource-aware operating systems
- Experimental analysis of the timing behavior of processors
- Methods and benchmarks for WCET analysis evaluation
- Case studies and industrial experiences of WCET analysis
- WCET analysis in the academic curriculum
Statements which are innovative, controversial, or that present new approaches are specially sought.
FOCUS OF THE 2016 EDITION
This year we feature papers that provide tools in open source and provide instructions how the evaluation results can be reproduced. The PC will explore those open source tools as part of the paper review process.
WORKSHOP STRUCTURE
The goal of the workshop is to bring together people from academia, tool vendors and users in industry who are interested in all aspects of timing predictability of real-time systems. The workshop fosters a highly interactive format with ample time for in-depth discussions. It provides a relaxed forum to present and discuss new ideas, new research directions, and to review current trends in this area. The presentations will be kept short to leave plenty of time for interaction of attendees.
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16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)
Toulouse, France | 5th July 2016 | http://wcet2016.compute.dtu.dk
in conjunction with the Euromicro Conference on Real-Time Systems (ECRTS)
WCET 2016 is kindly supported by TACLe (www.tacle.eu), an European COST-Action on Timing Analysis on Code-Level.
GOALS AND TOPICS
A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori. Perhaps paradoxically, this problem has become more difficult by the introduction of performance-enhancing architectural elements, such as caches, pipelines, and multi-threading, which introduce a large degree of uncertainty and make timing guarantees harder to provide.
The WCET workshop focuses on the analysis and design of timing-predictable systems, with a strong emphasis on worst-case execution time (WCET) analysis.
Topics of interest include all aspects of timing analysis and timing-predictability. This includes (but is not limited to):
- WCET analysis for multi-threaded and multi-core systems
- Low-level timing analysis, modeling and analysis of processor features
- Flow analysis for WCET, loop bounds, infeasible paths
- Measurement-based WCET analysis
- Different approaches to WCET computation
- Probabilistic timing analysis
- Tools for WCET analysis
- Integration of WCET and schedulability analysis
- Integration of WCET analysis in development processes
- Strategies to reduce the complexity of WCET analysis
- Processor and hardware design for timing predictability
- Program design for timing predictability
- Compiler-based optimization of worst-case timing
- Timing-predictable, resource-aware operating systems
- Experimental analysis of the timing behavior of processors
- Methods and benchmarks for WCET analysis evaluation
- Case studies and industrial experiences of WCET analysis
- WCET analysis in the academic curriculum
Statements which are innovative, controversial, or that present new approaches are specially sought.
FOCUS OF THE 2016 EDITION
This year we feature papers that provide tools in open source and provide instructions how the evaluation results can be reproduced. The PC will explore those open source tools as part of the paper review process.
WORKSHOP STRUCTURE
The goal of the workshop is to bring together people from academia, tool vendors and users in industry who are interested in all aspects of timing predictability of real-time systems. The workshop fosters a highly interactive format with ample time for in-depth discussions. It provides a relaxed forum to present and discuss new ideas, new research directions, and to review current trends in this area. The presentations will be kept short to leave plenty of time for interaction of attendees.