HEART 2017
Date: Jun 07, 2017 12:00 am – Jun 09, 2017 11:00 am
Location: Bochum, Germany
The 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART2017)
7-9 June 2017 | Bochum, Germany | http://www.isheart.org/HEART2017
Important dates:
- Submission deadline for conference papers: February 20, 2017
- Acceptance notification: April 15, 2017
- Camera-ready/Author registration: April 30, 2017
- Symposium dates: June 7-9, 2017
The 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART) is a forum to present and discuss new research on accelerators and the use of reconfigurable technologies for high-performance and/or power-efficient computation. Submissions are solicited on a wide variety of topics related to the acceleration for high-performance computation, including but not limited to:
- Architectures and systems:
- Novel systems/platforms for efficient acceleration based on FPGA, GPU, and other devices
- Heterogeneous processor architectures and systems for scalable, high-performance, high-reliability, and/or low-power computation
- Reconfigurable and configurable hardware and systems including IP-cores, embedded systems, SoCs, and cluster/grid/cloud computing systems for scalable, high-performance and/or low-power processing
- Custom computing system for domain-specific applications such as Big-data, multimedia, bioinformatics, cryptography, and more
- Novel architectures and device technologies that can be applied to efficient acceleration, including many-core/NoC architectures, 3D-stacking technologies and optical devices
- Software and applications:
- Novel applications of high-performance computing and Big-data processing with efficientacceleration and custom computing
- System software, compilers and programming languages for efficient accelerationsystems / platforms, including many-core processors, GPUs, FPGAs and otherreconfigurable /custom processors
- Run-time techniques for acceleration, including Just-in-Time compilation and dynamicpartial-reconfiguration
- Performance evaluation and analysis for efficient acceleration
- High-level synthesis and design methodologies for heterogeneous, reconfigurable and/orcustom processors/systems
Organizing Committee:
General co-chairs:
- Michael Huebner, Ruhr-University Bochum, DE
- Diana Goehringer, Ruhr-Universitat Bochum, DE
Technical program co-chairs:
- Holger Blume, Leibniz University Hannover, DE
- Martin Herbordt, Boston University, US
- Hiroki Nakahara, Tokyo Tech, JP
Publicity co-chairs:
- Kenji Kanazawa, University of Tsukuba, JP
- Brain Veale, IBM, US
- Gabriel Almeida, Harman International, DE
Finance and local arrangement chair:
- Linda Trogant, Ruhr-University Bochum, DE
Publication chair:
- Yuichiro Shibata, Nagasaki University, JP
Design contest chair:
- Donald Bailey, Donald Bailey, NZ
Submitted by Anonymous
on
Date: Jun 07, 2017 12:00 am – Jun 09, 2017 11:00 am
Location: Bochum, Germany
The 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART2017)
7-9 June 2017 | Bochum, Germany | http://www.isheart.org/HEART2017
Important dates:
- Submission deadline for conference papers: February 20, 2017
- Acceptance notification: April 15, 2017
- Camera-ready/Author registration: April 30, 2017
- Symposium dates: June 7-9, 2017
The 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART) is a forum to present and discuss new research on accelerators and the use of reconfigurable technologies for high-performance and/or power-efficient computation. Submissions are solicited on a wide variety of topics related to the acceleration for high-performance computation, including but not limited to:
- Architectures and systems:
- Novel systems/platforms for efficient acceleration based on FPGA, GPU, and other devices
- Heterogeneous processor architectures and systems for scalable, high-performance, high-reliability, and/or low-power computation
- Reconfigurable and configurable hardware and systems including IP-cores, embedded systems, SoCs, and cluster/grid/cloud computing systems for scalable, high-performance and/or low-power processing
- Custom computing system for domain-specific applications such as Big-data, multimedia, bioinformatics, cryptography, and more
- Novel architectures and device technologies that can be applied to efficient acceleration, including many-core/NoC architectures, 3D-stacking technologies and optical devices
- Software and applications:
- Novel applications of high-performance computing and Big-data processing with efficientacceleration and custom computing
- System software, compilers and programming languages for efficient accelerationsystems / platforms, including many-core processors, GPUs, FPGAs and otherreconfigurable /custom processors
- Run-time techniques for acceleration, including Just-in-Time compilation and dynamicpartial-reconfiguration
- Performance evaluation and analysis for efficient acceleration
- High-level synthesis and design methodologies for heterogeneous, reconfigurable and/orcustom processors/systems
Organizing Committee:
General co-chairs:
- Michael Huebner, Ruhr-University Bochum, DE
- Diana Goehringer, Ruhr-Universitat Bochum, DE
Technical program co-chairs:
- Holger Blume, Leibniz University Hannover, DE
- Martin Herbordt, Boston University, US
- Hiroki Nakahara, Tokyo Tech, JP
Publicity co-chairs:
- Kenji Kanazawa, University of Tsukuba, JP
- Brain Veale, IBM, US
- Gabriel Almeida, Harman International, DE
Finance and local arrangement chair:
- Linda Trogant, Ruhr-University Bochum, DE
Publication chair:
- Yuichiro Shibata, Nagasaki University, JP
Design contest chair:
- Donald Bailey, Donald Bailey, NZ
Submitted by Anonymous
on