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IEEE Workshop on Signal Processing Systems (SiPS 2017)

IEEE SiPS is a premier international forum collecting researchers and practitioners from industry and academia for exchanging the latest scientific and technical advances in the area of design and implementation of signal processing systems. It addresses current and future challenges and new directions in research and development of these systems. Prospective authors are invited to submit manuscripts on topics including, but not limited to:

Software Based Design and Implementation of Signal Processing Systems

  • Software solutions on programmable digital signal processors and systems
  • Application specific instruction-set processor (ASIP) architectures and systems
  • SIMD, VLIW and multi-core CPU architectures
  • Graphics processing unit (GPU) based massively parallel implementations
  • Embedded FPGA architectures

Hardware Based Design and Implementation of Signal Processing Systems

  • Low-power signal processing circuits and applications
  • High performance VLSI systems
  • VLSI designs for 100 Gbps and beyond networking systems
  • FPGA and reconfigurable architecture based systems
  • System-on-chip and network-on-chip
  • VLSI systems for wireless sensor network and RF identification systems

Emerging Technologies

  • Vehicular ad hoc networks (VANET)
  • Cognitive radio networks
  • Internet of Things (IoT)
  • Deep learning and reconfigurable/ASIC processors
  • Bio-inspired networks
  • Context-aware mobile networking
  • Wireless body area networks (WBANs)
  • Implantable communications
  • Tele-medicine/e-health networks

Signal Processing Application Systems

  • Audio, speech and language processing
  • Biomedical signal processing and bioinformatics
  • Image, video and multimedia signal processing
  • Information forensics, security and cryptography
  • Machine learning for signal processing
  • Sensing and sensor signal processing
  • Autonomous energy harvesting-based sensor networks
  • Signal processing for non-volatile memory system
  • Latency and power constrained signal processing techniques for high-speed networking
  • Wireless communications and networking
  • Coding and compression
  • Multiple-input-multiple-output (MIMO) and communication systems
  • Software defined radio

Signal Processing Compensation Techniques for Mixed-Signal Technologies

  • Digital compensation techniques for variations in silicon process, temperature, aging
  • Error detection and correction for volatile and non-volatile memories
  • Power reduction and SNR improvement for on- chip, off-chip interconnects and buses
  • Digital compensation signal processing for ADCs, power-amps, MEMS, power controllers

Design Methods of Signal Processing Algorithms and Architectures

  • Optimization of signal processing algorithms
  • Compilers and tools for signal processing systems
  • Algorithm transformation and algorithm-to- architecture mapping
  • Dataflow based design methodologies
  • Error-tolerant techniques for signal processing

General Chairs:

  • Ph. Coussy, U. Bretagne Sud, FR
  • W. Gross, McGill U., QC, CA

Program Chairs:

  • J. Takala, Tampere U. Tech., FI
  • A. Burg, EPFL, CH

Finance Chairs:

  • G. Gogniat, U. Bretagne Sud, FR
  • M. Mattavelli, EPFL, CH

Local Arrangements Chairs:

  • C. Chavet, U. Bretagne Sud, FR
  • J. Laurent, U. Bretagne Sud, FR

Publication and publicity chairs:

  • C. Jego, Bordeaux INP, FR
  • V. Lapotre, U. Bretagne Sud, FR

Special sessions chair:

  • E. Boutillon, U. Bretagne Sud, FR

Industrial liaison chairs:

  • K. Benkrid, ARM, UK
  • X. Zhang, SanDisk, US

Demo night chair:

  • M. Raulet, ATEME, FR

Web site:

  • K. Martin, U. Bretagne Sud, FR

Asian liaison:

  • A.-Y. Wu, NTU, TW

North-America liaison:

  • J. Cavallaro, Rice U., TX, US

Sponsored by:

  • IEEE Signal Processing Society
  • IEEE Circuits and Systems Society
Event Details
Lorient, France