NoCArc 2017
10th International Workshop on Network on Chip Architectures
To be held in conjunction with IEEE/ACM MICRO-50
G E N E R A L I N F O R M A T I O N
Current multicore architectures formed by tens of processing cores will be soon replaced by the next generation of manycore architectures with hundreds of cores. In fact, the International Technology Roadmap for Semiconductors foresees that the number of Processing Elements (PEs) that will be integrated into a System-on-Chip (SoC) will be in the order of thousand within the 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global interconnections become the major bottleneck. The Network-on-Chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects, and integration of large number of PEs on a chip.
The goal of NoCArc workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. The workshop will focus on issues related to design, analysis and testing of on-chip networks.
A R E A S O F I N T E R E S T
The workshop will focus on issues related to design, analysis and testing of on-chip networks. The topics of specific interest for the workshop include, but are not limited to:
NoC Architecture and Implementation
- Topologies, routing, flow control
- Managing QoS
- Timing, synchronous/asynchronous communication
- Reliability issues
- Design methodologies and tools
- Signaling & circuit design for NoC links
- NoC Analysis and Verification
Power, energy and thermal issues
- Benchmarking and experience with NoC-based systems
- Modeling, simulation, and synthesis
- Verification, debug and test
- Metrics and benchmarks
- NoC Application
Mapping of applications onto NoCs
- NoC case studies, application-specific NoC design
- NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
- NoC designs for heterogeneous systems
- On-Chip Communication Optimization
Communication efficient algorithms
- Multi/many-core communication workload characterization and evaluation
- Energy efficient NoCs and energy minimization
- NoC at System-level
Design of memory subsystem
- NoC support for memory and cache access
- OS support for NoCs
- Programming models including shared memory, message passing and novel programming models
- Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks
Emerging NoC Technologies
- Wireless, Optical, and RF
- NoCs for 3D and 2.5D packages
Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.
O R G A N I Z E R S
STEERING COMMITTEE
- Maurizio Palesi, Univ. of Catania, Italy
- Masoud Daneshtalab, Univ. of Turku, Finland and KTH, Sweden
- Xiaohang Wang, South China University of Technology, China
GENERAL CHAIRS
- Davide Patti, Univ. of Catania, Italy
TPC CHAIRS
- Masoumeh Ebrahimi, Univ. of Turku, Finland
- Thomas Hollstein, Tallinn University of Technology
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10th International Workshop on Network on Chip Architectures
To be held in conjunction with IEEE/ACM MICRO-50
G E N E R A L I N F O R M A T I O N
Current multicore architectures formed by tens of processing cores will be soon replaced by the next generation of manycore architectures with hundreds of cores. In fact, the International Technology Roadmap for Semiconductors foresees that the number of Processing Elements (PEs) that will be integrated into a System-on-Chip (SoC) will be in the order of thousand within the 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global interconnections become the major bottleneck. The Network-on-Chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects, and integration of large number of PEs on a chip.
The goal of NoCArc workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. The workshop will focus on issues related to design, analysis and testing of on-chip networks.
A R E A S O F I N T E R E S T
The workshop will focus on issues related to design, analysis and testing of on-chip networks. The topics of specific interest for the workshop include, but are not limited to:
NoC Architecture and Implementation
- Topologies, routing, flow control
- Managing QoS
- Timing, synchronous/asynchronous communication
- Reliability issues
- Design methodologies and tools
- Signaling & circuit design for NoC links
- NoC Analysis and Verification
Power, energy and thermal issues
- Benchmarking and experience with NoC-based systems
- Modeling, simulation, and synthesis
- Verification, debug and test
- Metrics and benchmarks
- NoC Application
Mapping of applications onto NoCs
- NoC case studies, application-specific NoC design
- NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
- NoC designs for heterogeneous systems
- On-Chip Communication Optimization
Communication efficient algorithms
- Multi/many-core communication workload characterization and evaluation
- Energy efficient NoCs and energy minimization
- NoC at System-level
Design of memory subsystem
- NoC support for memory and cache access
- OS support for NoCs
- Programming models including shared memory, message passing and novel programming models
- Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks
Emerging NoC Technologies
- Wireless, Optical, and RF
- NoCs for 3D and 2.5D packages
Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.
O R G A N I Z E R S
STEERING COMMITTEE
- Maurizio Palesi, Univ. of Catania, Italy
- Masoud Daneshtalab, Univ. of Turku, Finland and KTH, Sweden
- Xiaohang Wang, South China University of Technology, China
GENERAL CHAIRS
- Davide Patti, Univ. of Catania, Italy
TPC CHAIRS
- Masoumeh Ebrahimi, Univ. of Turku, Finland
- Thomas Hollstein, Tallinn University of Technology