RAPIDO '18
Date: Jan 22, 2018 1:00 am – Jan 22, 2018 2:00 pm
Location: Manchester, UK
10th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools - RAPIDO
co-located with HiPEAC Conference
The focus of the RAPIDO workshop is on methods and tools for rapid simulation and performance evaluation in embedded and high performance system design. Given continuous advances in chip technology, it is to be expected that future-generation processors will integrate numerous units on a single die, including multiple (heterogeneous) processor cores, multiple levels of (shared/private) caches or memories, and dedicated accelerators, which will be glued together through a network on-chip (NoC).
The design space is huge though and several design metrics should be considered as well for selecting the optimal system configuration. Despite several years of research, the early stage design phase still requires to be supported by innovative design methodologies and tools for simulation, exploartion and performance evaluation. RAPIDO seeks for original research papers that face this challenge for embedded and high performance computing systems.
Topics of interest include, but are not limited to:
- Rapid simulation techniques targeted at novel architectures: Multi-cores, 3D-architectures, FPGA based heterogeneous Multi-cores/MPSoC, ...
- Variability and power/energy consumption in performance estimation and simulation techniques.
- High-level abstraction modeling, e.g., Transactional Level Modeling (TLM), Analytical Modeling, Trace-Driven Simulation …
- Design space exploration (DSE) for heterogeneous high-performance and embedded systems.
- Dynamic binary translation for fast simulation and DSE
- Experience reports using existing simulators and tools
- Benchmarking and simulator validation
- Early stage prototype of innovative architectures
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10th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools - RAPIDO
co-located with HiPEAC Conference
The focus of the RAPIDO workshop is on methods and tools for rapid simulation and performance evaluation in embedded and high performance system design. Given continuous advances in chip technology, it is to be expected that future-generation processors will integrate numerous units on a single die, including multiple (heterogeneous) processor cores, multiple levels of (shared/private) caches or memories, and dedicated accelerators, which will be glued together through a network on-chip (NoC).
The design space is huge though and several design metrics should be considered as well for selecting the optimal system configuration. Despite several years of research, the early stage design phase still requires to be supported by innovative design methodologies and tools for simulation, exploartion and performance evaluation. RAPIDO seeks for original research papers that face this challenge for embedded and high performance computing systems.
Topics of interest include, but are not limited to:
- Rapid simulation techniques targeted at novel architectures: Multi-cores, 3D-architectures, FPGA based heterogeneous Multi-cores/MPSoC, ...
- Variability and power/energy consumption in performance estimation and simulation techniques.
- High-level abstraction modeling, e.g., Transactional Level Modeling (TLM), Analytical Modeling, Trace-Driven Simulation …
- Design space exploration (DSE) for heterogeneous high-performance and embedded systems.
- Dynamic binary translation for fast simulation and DSE
- Experience reports using existing simulators and tools
- Benchmarking and simulator validation
- Early stage prototype of innovative architectures