WCET 2018
Date: Jul 03, 2018 12:00 am – Jul 03, 2018 11:00 am
Location: Barcelona, Spain
18th International Workshop on Worst-Case Execution Time Analysis (WCET 2018)
co-located with the Euromicro Conference on Real-Time Systems (ECRTS 2018)
The International Workshop on Worst-Case Execution Time Analysis (WCET 2018) focuses on the analysis and design of real-time systems in a broad sense, with a particular emphasis on techniques to analyze the worst-case execution time (WCET) of real-time software. The workshop covers topics related to hard and soft real-time systems, program analysis, timing analysis, as well as (time-predictable) hardware designs and operating systems.
GOALS AND TOPICS
A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy timing requirements, often under resources constraints. The analysis of such real-time systems is often challenging due to the interaction of the physical environment with the system's software, which in turn interacts with the underlying hardware as well as other software components. All these interactions make it difficult in practice to guarantee that a system meets all its timing requirements. Designers and engineers thus strive for their systems to be timing-predictable and analyzable, i.e., facilitate the verification of the system's timing behavior.
The WCET workshop covers all aspects related to timing analysis and the design of timing-predictable systems, with a particular emphasis on worst-case execution time (WCET) analysis.
Topics of interest include, but are not limited to:
- Integration of WCET analysis in development processes
- Integration of WCET and schedulability analysis
- Experimental analysis of the timing behavior of processors
- Processor and hardware design for timing predictability
- Timing-predictable, resource-aware operating systems
- Program design for timing predictability
- Flow analysis for WCET, loop bounds, infeasible paths
- Low-level timing analysis, modeling and analysis of processor features
- WCET analysis for multi-threaded and multi-core systems
- Measurement-based WCET analysis
- Tools for WCET analysis
- Strategies to reduce the complexity of WCET analysis
- Compiler-based optimization of worst-case timing
- Methods and benchmarks for WCET analysis evaluation
- Case studies and industrial experiences of WCET analysis
- WCET analysis in the academic curriculum
Statements which are innovative, controversial, or that present new approaches are specially sought.
PROGRAM CHAIR
Florian Brandner, Télécom ParisTech, Université Paris-Saclay
PROGRAM COMMITTEE
- Armelle Bonenfant, Université Toulouse III - Paul Sabatier, France
- Björn Lisper, Mälardalen University, Sweden
- Claire Maiza, Grenoble INP/Verimag, France
- Clément Ballabriga, Lille 1 University, France
- Jan Reineke, Saarland University, Germany
- Jakob Zwirchmayr, TTTech Computertechnik AG - Automotive, Austria
- Jaume Abella, Barcelona Supercomputing Center, Spain
- Jörg Mische, Augsburg University, Germany
- Kartik Nagar, Purdue University, United States
- Luca Santinelli, ONERA, France
- Martin Schoeberl, Technical University of Denmark, Denmark
- Peter Ulbrich, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany
- Simon Wegener, AbsInt Angewandte Informatik GmbH, Germany
- Tullio Vardanega, University of Padua, Italy
- Xenofon Koutsoukos, Vanderbilt University, USA
STEERING COMMITTEE
- Björn Lisper, Mälardalen University, Sweden
- Isabelle Puaut, University of Rennes I/IRISA, France
- Jan Reineke, Saarland University, Germany
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on
18th International Workshop on Worst-Case Execution Time Analysis (WCET 2018)
co-located with the Euromicro Conference on Real-Time Systems (ECRTS 2018)
The International Workshop on Worst-Case Execution Time Analysis (WCET 2018) focuses on the analysis and design of real-time systems in a broad sense, with a particular emphasis on techniques to analyze the worst-case execution time (WCET) of real-time software. The workshop covers topics related to hard and soft real-time systems, program analysis, timing analysis, as well as (time-predictable) hardware designs and operating systems.
GOALS AND TOPICS
A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy timing requirements, often under resources constraints. The analysis of such real-time systems is often challenging due to the interaction of the physical environment with the system's software, which in turn interacts with the underlying hardware as well as other software components. All these interactions make it difficult in practice to guarantee that a system meets all its timing requirements. Designers and engineers thus strive for their systems to be timing-predictable and analyzable, i.e., facilitate the verification of the system's timing behavior.
The WCET workshop covers all aspects related to timing analysis and the design of timing-predictable systems, with a particular emphasis on worst-case execution time (WCET) analysis.
Topics of interest include, but are not limited to:
- Integration of WCET analysis in development processes
- Integration of WCET and schedulability analysis
- Experimental analysis of the timing behavior of processors
- Processor and hardware design for timing predictability
- Timing-predictable, resource-aware operating systems
- Program design for timing predictability
- Flow analysis for WCET, loop bounds, infeasible paths
- Low-level timing analysis, modeling and analysis of processor features
- WCET analysis for multi-threaded and multi-core systems
- Measurement-based WCET analysis
- Tools for WCET analysis
- Strategies to reduce the complexity of WCET analysis
- Compiler-based optimization of worst-case timing
- Methods and benchmarks for WCET analysis evaluation
- Case studies and industrial experiences of WCET analysis
- WCET analysis in the academic curriculum
Statements which are innovative, controversial, or that present new approaches are specially sought.
PROGRAM CHAIR
Florian Brandner, Télécom ParisTech, Université Paris-Saclay
PROGRAM COMMITTEE
- Armelle Bonenfant, Université Toulouse III - Paul Sabatier, France
- Björn Lisper, Mälardalen University, Sweden
- Claire Maiza, Grenoble INP/Verimag, France
- Clément Ballabriga, Lille 1 University, France
- Jan Reineke, Saarland University, Germany
- Jakob Zwirchmayr, TTTech Computertechnik AG - Automotive, Austria
- Jaume Abella, Barcelona Supercomputing Center, Spain
- Jörg Mische, Augsburg University, Germany
- Kartik Nagar, Purdue University, United States
- Luca Santinelli, ONERA, France
- Martin Schoeberl, Technical University of Denmark, Denmark
- Peter Ulbrich, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany
- Simon Wegener, AbsInt Angewandte Informatik GmbH, Germany
- Tullio Vardanega, University of Padua, Italy
- Xenofon Koutsoukos, Vanderbilt University, USA
STEERING COMMITTEE
- Björn Lisper, Mälardalen University, Sweden
- Isabelle Puaut, University of Rennes I/IRISA, France
- Jan Reineke, Saarland University, Germany