Visible to the public Biblio

Filters: Author is Bhunia, S.  [Clear All Filters]
2015-05-06
Bhunia, S., Hsiao, M.S., Banga, M., Narasimhan, S..  2014.  Hardware Trojan Attacks: Threat Analysis and Countermeasures. Proceedings of the IEEE. 102:1229-1247.

Security of a computer system has been traditionally related to the security of the software or the information being processed. The underlying hardware used for information processing has been considered trusted. The emergence of hardware Trojan attacks violates this root of trust. These attacks, in the form of malicious modifications of electronic hardware at different stages of its life cycle, pose major security concerns in the electronics industry. An adversary can mount such an attack with an objective to cause operational failure or to leak secret information from inside a chip-e.g., the key in a cryptographic chip, during field operation. Global economic trend that encourages increased reliance on untrusted entities in the hardware design and fabrication process is rapidly enhancing the vulnerability to such attacks. In this paper, we analyze the threat of hardware Trojan attacks; present attack models, types, and scenarios; discuss different forms of protection approaches, both proactive and reactive; and describe emerging attack modes, defenses, and future research pathways.
 

2017-05-17
Xiao, K., Forte, D., Jin, Y., Karri, R., Bhunia, S., Tehranipoor, M..  2016.  Hardware Trojans: Lessons Learned After One Decade of Research. ACM Trans. Des. Autom. Electron. Syst.. 22:6:1–6:23.

Given the increasing complexity of modern electronics and the cost of fabrication, entities from around the globe have become more heavily involved in all phases of the electronics supply chain. In this environment, hardware Trojans (i.e., malicious modifications or inclusions made by untrusted third parties) pose major security concerns, especially for those integrated circuits (ICs) and systems used in critical applications and cyber infrastructure. While hardware Trojans have been explored significantly in academia over the last decade, there remains room for improvement. In this article, we examine the research on hardware Trojans from the last decade and attempt to capture the lessons learned. A comprehensive adversarial model taxonomy is introduced and used to examine the current state of the art. Then the past countermeasures and publication trends are categorized based on the adversarial model and topic. Through this analysis, we identify what has been covered and the important problems that are underinvestigated. We also identify the most critical lessons for those new to the field and suggest a roadmap for future hardware Trojan research.

2017-10-27
Ismari, D., Plusquellic, J., Lamech, C., Bhunia, S., Saqib, F..  2016.  On Detecting Delay Anomalies Introduced by Hardware Trojans. Proceedings of the 35th International Conference on Computer-Aided Design. :44:1–44:7.

A hardware Trojan (HT) detection method is presented that is based on measuring and detecting small systematic changes in path delays introduced by capacitive loading effects or series inserted gates of HTs. The path delays are measured using a high resolution on-chip embedded test structure called a time-to-digital converter (TDC) that provides approx. 25 ps of timing resolution. A calibration method for the TDC as well as a chip-averaging technique are demonstrated to nearly eliminate chip-to-chip and within-die process variation effects on the measured path delays across chips. This approach significantly improves the correlation between Trojan-free chips and a simulation-based golden model. Path delay tests are applied to multiple copies of a 90nm custom ASIC chip having two copies of an AES macro. The AES macros are exact replicas except for the insertion of several additional gates in the second hardware copy, which are designed to model HTs. Simple statistical detection methods are used to isolate and detect systematic changes introduced by these additional gates. We present hardware results which demonstrate that our proposed chip-averaging and calibration techniques in combination with a single nominal simulation model can be used to detect small delay anomalies introduced by the inserted gates of hardware Trojans.

2017-12-12
Contreras, G. K., Nahiyan, A., Bhunia, S., Forte, D., Tehranipoor, M..  2017.  Security vulnerability analysis of design-for-test exploits for asset protection in SoCs. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC). :617–622.

SoCs implementing security modules should be both testable and secure. Oversights in a design's test structure could expose internal modules creating security vulnerabilities during test. In this paper, for the first time, we propose a novel automated security vulnerability analysis framework to identify violations of confidentiality, integrity, and availability policies caused by test structures and designer oversights during SoC integration. Results demonstrate existing information leakage vulnerabilities in implementations of various encryption algorithms and secure microprocessors. These can be exploited to obtain secret keys, control finite state machines, or gain unauthorized access to memory read/write functions.

2018-01-23
Karam, R., Hoque, T., Ray, S., Tehranipoor, M., Bhunia, S..  2017.  MUTARCH: Architectural diversity for FPGA device and IP security. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC). :611–616.
Field Programmable Gate Arrays (FPGAs) are being increasingly deployed in diverse applications including the emerging Internet of Things (IoT), biomedical, and automotive systems. However, security of the FPGA configuration file (i.e. bitstream), especially during in-field reconfiguration, as well as effective safeguards against unauthorized tampering and piracy during operation, are notably lacking. The current practice of bitstreram encryption is only available in high-end FPGAs, incurs unacceptably high overhead for area/energy-constrained devices, and is susceptible to side channel attacks. In this paper, we present a fundamentally different and novel approach to FPGA security that can protect against all major attacks on FPGA, namely, unauthorized in-field reprogramming, piracy of FPGA intellectual property (IP) blocks, and targeted malicious modification of the bitstream. Our approach employs the security through diversity principle to FPGA, which is often used in the software domain. We make each device architecturally different from the others using both physical (static) and logical (time-varying) configuration keys, ensuring that attackers cannot use a priori knowledge about one device to mount an attack on another. It therefore mitigates the economic motivation for attackers to reverse engineering the bitstream and IP. The approach is compatible with modern remote upgrade techniques, and requires only small modifications to existing FPGA tool flows, making it an attractive addition to the FPGA security suite. Our experimental results show that the proposed approach achieves provably high security against tampering and piracy with worst-case 14% latency overhead and 13% area overhead.
2018-05-01
Zhang, F., Masna, N. V. R., Bhunia, S., Chen, C., Mandal, S..  2017.  Authentication and Traceability of Food Products through the Supply Chain Using NQR Spectroscopy. 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS). :1–4.

Maintaining the security and integrity of our food supply chain has emerged as a critical need. In this paper, we describe a novel authentication approach that can significantly improve the security of the food supply chain. It relies on applying nuclear quadrupole resonance (NQR) spectroscopy to authenticate the contents of packaged food products. NQR is a non-invasive, non-destructive, and quantitative radio frequency (RF) spectroscopic technique. It is sensitive to subtle features of the solid-state chemical environment such that signal properties are influenced by the manufacturing process, thus generating a manufacturer-specific watermark or intrinsic tag for the product. Such tags enable us to uniquely characterize and authenticate products of identical composition but from different manufacturers based on their NQR signal parameters. These intrinsic tags can be used to verify the integrity of a product and trace it through the supply chain. We apply a support vector machine (SVM)-based classification approach that trains the SVM with measured NQR parameters and then authenticates food products by checking their test responses. Measurement on an example substance using semi-custom hardware shows promising results (95% classification accuracy) which can be further improved with improved instrumentation.

2018-06-20
Bhunia, S., Sengupta, S..  2017.  Distributed adaptive beam nulling to mitigate jamming in 3D UAV mesh networks. 2017 International Conference on Computing, Networking and Communications (ICNC). :120–125.

With the advancement of unmanned aerial vehicles (UAV), 3D wireless mesh networks will play a crucial role in next generation mission critical wireless networks. Along with providing coverage over difficult terrain, it provides better spectral utilization through 3D spatial reuse. However, being a wireless network, 3D meshes are vulnerable to jamming/disruptive attacks. A jammer can disrupt the communication, as well as control of the network by intelligently causing interference to a set of nodes. This paper presents a distributed mechanism of avoiding jamming attacks by means of 3D spatial filtering where adaptive beam nulling is used to keep the jammer in null region in order to bypass jamming. Kalman filter based tracking mechanism is used to estimate the most likely trajectory of the jammer from noisy observation of the jammer's position. A beam null border is determined by calculating confidence region of jammer's current and next position estimates. An optimization goal is presented to calculate optimal beam null that minimizes the number of deactivated links while maximizing the higher value of confidence for keeping the jammer inside the null. The survivability of a 3D mesh network with a mobile jammer is studied through simulation that validates an 96.65% reduction in the number of jammed nodes.