Visible to the public Biblio

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Ansari, Azadeh.  2019.  Single Crystalline Scandium Aluminum Nitride: An Emerging Material for 5G Acoustic Filters. 2019 IEEE MTT-S International Wireless Symposium (IWS). :1–3.
Emerging next generation wireless communication devices call for high-performance filters that operate at 3-10 GHz frequency range and offer low loss, small form factor, wide bandwidth and steep skirts. Bulk and surface acoustic wave devices have been long used in the RF front-end for filtering applications, however their operation frequencies are mostly below 2.6 GHz band. To scale up the frequency of the filters, the thickness of the piezoelectric material needs to be reduced to sub-micron ranges. One of the challenges of such scaling is maintaining high electromechanical coupling as the film thickness decreases, which in turn, determines the filter bandwidth.Aluminum Nitride (AlN) - popular in today's film bulk acoustic resonators (FBARs) and mostly deposited using sputtering techniques-shows degraded crystal quality and poor electromechanical coupling when the thickness of AlN film is smaller than 1 μm.In this work, we propose using high-quality single-crystalline AlN and Scandium (Sc)-doped AlN epi-layers grown on Si substrates, wherein high crystal quality is maintained for ultra-thin films of only 400 nm thickness. Experimental results verify improved kt2 for 3-10 GHz resonators, with quality factors of the order of 250 and kt2 values of up to 5%based on bulk acoustic wave resonators. The experimental results suggest that single-crystal Sc-AlN is a great material candidate for 5G resonators and filters.
Medury, Aditya Sankar, Kansal, Harshit.  2019.  Quantum Confinement Effects and Electrostatics of Planar Nano-Scale Symmetric Double-Gate SOI MOSFETs. 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). :1-3.

The effects of quantum confinement on the charge distribution in planar Double-Gate (DG) SOI (Siliconon-Insulator) MOSFETs were examined, for sub-10 nm SOI film thicknesses (tsi $łeq$ 10 nm), by modeling the potential experienced by the charge carriers as that of an an-harmonic oscillator potential, consistent with the inherent structural symmetry of nanoscale symmetric DGSOI MOSFETs. By solving the 1-D Poisson's equation using this potential, the results obtained were validated through comparisons with TCAD simulations. The present model satisfactorily predicted the electron density and channel charge density for a wide range of SOI channel thicknesses and gate voltages.

Ye, J., Yang, Y., Gong, Y., Hu, Y., Li, X..  2018.  Grey Zone in Pre-Silicon Hardware Trojan Detection. 2018 IEEE International Test Conference in Asia (ITC-Asia). :79-84.

Pre-Silicon hardware Trojan detection has been studied for years. The most popular benchmark circuits are from the Trust-Hub. Their common feature is that the probability of activating hardware Trojans is very low. This leads to a series of machine learning based hardware Trojan detection methods which try to find the nets with low signal probability of 0 or 1. On the other hand, it is considered that, if the probability of activating hardware Trojans is high, these hardware Trojans can be easily found through behaviour simulations or during functional test. This paper explores the "grey zone" between these two opposite scenarios: if the activation probability of a hardware Trojan is not low enough for machine learning to detect it and is not high enough for behaviour simulation or functional test to find it, it can escape from detection. Experiments show the existence of such hardware Trojans, and this paper suggests a new set of hardware Trojan benchmark circuits for future study.

Keeler, G. A., Campione, S., Wood, M. G., Serkland, D. K., Parameswaran, S., Ihlefeld, J., Luk, T. S., Wendt, J. R., Geib, K. M..  2017.  Reducing optical confinement losses for fast, efficient nanophotonic modulators. 2017 IEEE Photonics Society Summer Topical Meeting Series (SUM). :201–202.

We demonstrate high-speed operation of ultracompact electroabsorption modulators based on epsilon-near-zero confinement in indium oxide (In$_\textrm2$$_\textrm3$\$) on silicon using field-effect carrier density tuning. Additionally, we discuss strategies to enhance modulator performance and reduce confinement-related losses by introducing high-mobility conducting oxides such as cadmium oxide (CdO).

Yang, L., Murmann, B..  2017.  SRAM voltage scaling for energy-efficient convolutional neural networks. 2017 18th International Symposium on Quality Electronic Design (ISQED). :7–12.

State-of-the-art convolutional neural networks (ConvNets) are now able to achieve near human performance on a wide range of classification tasks. Unfortunately, current hardware implementations of ConvNets are memory power intensive, prohibiting deployment in low-power embedded systems and IoE platforms. One method of reducing memory power is to exploit the error resilience of ConvNets and accept bit errors under reduced supply voltages. In this paper, we extensively study the effectiveness of this idea and show that further savings are possible by injecting bit errors during ConvNet training. Measurements on an 8KB SRAM in 28nm UTBB FD-SOI CMOS demonstrate supply voltage reduction of 310mV, which results in up to 5.4× leakage power reduction and up to 2.9× memory access power reduction at 99% of floating-point classification accuracy, with no additional hardware cost. To our knowledge, this is the first silicon-validated study on the effect of bit errors in ConvNets.

Perez, R..  2015.  Silicon systems security and building a root of trust. 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC). :1–4.

This paper briefly presents a position that hardware-based roots of trust, integrated in silicon with System-on-Chip (SoC) solutions, represent the most current stage in a progression of technologies aimed at realizing the most foundational computer security concepts. A brief look at this historical progression from a personal perspective is followed by an overview of more recent developments, with particular focus on a root of trust for cryptographic key provisioning and SoC feature management aimed at achieving supply chain assurances and serves as a basis for trust that is linked to properties enforced in hardware. The author assumes no prior knowledge of these concepts and developments by the reader.