Visible to the public SOCC 2020 - VirtualConflict Detection Enabled

33rd IEEE International System-on-Chip Conference (SOCC 2020)

Multibillion transistor System on Chip (SoC) devices, comprised of digital, analog, RF, optical, and Micro-Electro-Mechanical Systems (MEMS), are integral parts of ubiquitous communication, computing, entertainment, medical, logistics and carrier products. SoC has been the enabling technology and main thrust behind the evolution of the Internet into a global, cloud based communication and economic paradigm. Recent advances in systems, deep-submicron, nano process, and quantum-based technology are unleashing new opportunities, and also new challenges. These challenges include managing design and verification complexity, EDAtools, on-chip communication, design reuse, handling inevitable faults, and the efficient integration of emerging MEMS and nano components into next generation SoCs.

For more than 30 years the IEEE International System-on-Chip Conference (SOCC) has been the premier forum for sharing the latest advancements in SoC architecture, systems, logic and circuit design, process technology, test, design tools, and applications. We proudly continue this tradition with the 2020 conference.

The 33rd SOCC offers a three-day technical program including keynote and plenary speeches, oral and poster presentations, hot-topic panel sessions, and tutorials held by experts in the field. In addition, SOCC has a long tradition of high-class social events complementing the technical program, helping you to discuss your work with your colleagues, and enhancing your professional network.

For the first time in its history, SOCC will be held as a fully virtual, on-line event, with a mixture of pre-recorded presentations and live sessions.

Areas of Interest

Papers are invited which address new and previously unpublished results in all areas related to SoC,
including but not limited to:

Circuits and Systems:

  • RF, analog, mixed-signal -- Biomedical -- Wireline & wireless communication -- Digital signal processing (DSP) -- Memory systems -- Reconfigurable and programmable circuits

Low Power Design:

  • "Green" circuits & systems -- Low power methodologies -- Power/energy/ thermal aware architecture design -- Multi-domain power/energy management -- Energy harvesting

MPSoC Architectures:

  • On-chip interconnect -- Network on Chip (NoC) and multicore architectures -- Memory architecture for multicore computing -- 3D-IC -- Heterogeneous computing -- Parallel programming and software models

Design Methodologies:

  • HW-SW co-design, reconfiguration and debug -- System level design methodology and tools -- Heterogeneous design flows -- Design validation and verification -- Design for Testability, test synthesis, embedded test

Application Specific Design:

  • SoC for automotive systems -- Embedded computing and Internet of Things (IoT) -- Highperformance mobile SoCs -- Security -- Real-time, high reliability and safety SoCs -- Imaging and Vision -- Cloud Solutions

Emerging and Evolutionary Solutions:

  • Many-core architectures -- General purpose GPU (GPGPU) computing -- FPGA accelerated computing -- Server on a Chip -- Cortical processors -- Neuronal and neuromorphic computing -- Quantum computing -- Futuristic development and optimization tools.

SoCs for IoT and Intelligent Systems:

  • Evolvable and reconfigurable architectures -- Self-healing SoCs -- Architectures for intelligent hardware systems -- On-chip learning and adaption -- Neuromorphic chips -- Low-power and low-area SoCs for IoT


  • Three-day technical program
  • Full day of tutorials
  • Panel discussion, Design Track
  • Special Sessions, Social Events

Organizing Committee

General Chairs:

  • Danella Zhao, ODU
  • Venkatesan Muthukumar, UNLV

Technical Program Co-Chairs:

  • Gang Qu, University of Maryland
  • Jinjun Xiong, IBM, USA

Panel Co-Chairs:

  • Jurgen Becker, KIT, Germany
  • Magdy Bayoumi, UL Lafayette

Tutorial Co-Chairs:

  • Lan-Da Van, NCTU, Taiwan
  • Selcuk Kose, Univ. of Rochester, USA

Special Session Co-Chairs:

  • Arindam Basu, NTU, Singapore
  • Yiyu Shi, Univ. of Notre Dame

Publicity Co-Chairs:

  • Sakir Sezer, Queen's Univ. Belfast, UK
  • Andrew Marshall, UT Dallas
  • Norbert Wehn, Univ. Kaiserslautern, DE

Finance Chair:

  • Ramalingam Sridhar, SUNY at Buffalo

Registration Chair, Finance Co-Chair:

  • Thomas Buchner, IBM, Germany

IEEE CAS Liaison:

  • Mircea Stan, University of Virginia

Industrial Liaison:

  • Ram Krishnamurthy, Intel, USA
Event Details