PATMOS 2013
Date: Sep 09, 2013 1:30 am – Sep 11, 2013 7:30 pm
Location: Karlsruhe, Germany
The International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2013 is the 23nd in a series of international workshops. The PATMOS meeting has evolved into a leading scientific event where industry and academia meet to discuss power and timing aspects in modern integrated circuit and system design. Both Universities and Companies are invited to participate.
The PATMOS objective is to provide a forum to discuss and investigate emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems, including reconfigurable hardware such as FPGA’s. The technical program will focus on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization.
Topics of Interest
Authors are invited to submit manuscripts of original unpublished research. This year a focus is on power-efficiency. The topics of interest include, but are not limited to:
Reliability and Technology Variations
• Modeling and simulation in the presence of variability
• Variation-aware circuit design
• Reliability issues in nanoscale circuits
• Soft errors and radiation hardening
• Methods and Architectures for fault dependability
• Resilient hardware/software architectures
• Design for self adaptive circuits and systems
• Sensors for power, variability, temperature, and aging
Low Power and Thermal-aware Design
• Design techniques for thermal-aware and low power circuits and systems
• Power/thermal-aware synthesis and floorplanning
• Policies for power and thermal optimization
• Power/Thermal Estimation and Optimization
• Power/Thermal-aware architectures
• Hardware-software interaction for power/temperature minimization
• Energy-harvesting
• Low Power Systems: wireless sensor networks, mobile computing
Compilers, operating systems and runtime systems
• Power efficiency through parallelizing compilers or parallel programming
• Concepts for programming novel multi-core architectures
• Real-time system compilers, operating systems and run-time systems
FPGAs and GPU-based accelerators
• Novel accelerator-based architectures and architectural features
• High-Level Abstractions and CAD tools for using accelerators
• Neuro-Inspired Accelerators for Computing
• Customized processor instruction sets
• Compilers optimizing for dynamically reconfigurable processor arrays (DRPAs)
• Case studies and challenges on DRPAs and accelerators
Power-efficient High-performance ICT and Data Centers
• Supercomputing: compilers, operating systems, run time systems
• Hardware-software interaction for low power high-performance
• Modeling and analysis of energy costs for ICT subsystems and infrastructures
• Power analysis for data centers, supercomputers, communication networks
• Cross layer approaches and new paradigms for power efficiency in ICT
• Power-efficient I/O interfaces and NoC design
• Low power high performance in extreme scale supercomputing
• Heterogeneous HPC by new storage technologies
• Case studies: test cases, or design study challenges on data stations or supercomputers
Application-specific power efficiency by algorithmic and analytic efforts
• Banking, financial modeling and financial database acceleration
• Social networks, games, entertainment, ambient intelligence, ubiquitous and wearable computing
• Bioinformatics, bio-inspired, medical, and genetics systems and life sciences
• Physics and astronomy, weather prediction, oil and gas exploration, and more
• Security systems, cryptography, object recognition and tracking, global navigation satellite systems
• Audio/video, imaging, smart cameras, PDAs, smart image sensors, Reconfigurable Video Coding (RVC), etc. Aerospace, avionics, automotive and railway, and many other application areas
Case studies
• ICT, wireless sensor networks, wireless health, green computing, ultra low-power embedded systems, displays
• Examples, studies or challenges presenting innovative solutions for thermal and power efficiency
• Studies and experiences in using Azido
• Studies about power efficiency in extreme scale supercomputing projects
• Studies on energy efficiency by paradigm shift, by heterogeneous solutions or new storage technologies
• Case Studies on power efficiency of data stations
New directions in CS Education
• Roadmap of reconfigurable computing: compiled accelerators, ASICs and ASIPs
• New concepts in teaching, in tutorials, novel curricula and laboratories
• Industry and academic collaborative programs
• Design techniques for thermal and low power circuits and systems at all levels of abstraction
General co-chairs:
Jürgen Becker (becker@kit.edu)
Reiner Hartenstein (reiner@hartenstein.de)
Program co-chairs:
Jörg Henkel (henkel@kit.edu)
Alex Yakovlev ( Alex.Yakovlev@newcastle.ac.uk)
Publications chair:
Jian-Jia Chen (jian-jia.chen@kit.edu)
Publicity co-chairs:
Michael Hübner ( michael.huebner@rub.de)
Ricardo Reis ( reis@inf.ufrgs.br)
Local arrangements:
Lars Bauer (lars.bauer@kit.edu)
Oliver Sander (oliver.sander@kit.edu)
General chair VARI 2013:
Nadine Azemard (azemard@lirmm.fr)
Jörg Henkel (henkel@kit.edu)
Steering committee
Antonio J. Acosta, Univ. Sevilla, Spain
David Atienza, EPFL, Switzerland
Jose Luis Ayala, Universidad Complutense de Madrid, Spain
Nadine Azemard, Univ. Montpellier, France
Jürgen Becker Karlsruhe Institute of Technology, Germany
Joan Figueras, Univ. Catalunya, Spain
Reiner Hartenstein,TU Kaiserslautern, Germany
Jorge Juan-Chico, Univ. Sevilla, Spain
Rene van Leuken, TU Delft, The Netherlands
Enrico Macii, Politecnico di Torino, Italy
Philippe Maurine, Univ. Montpellier, France
Jose Monteiro, INESC-ID / IST, Portugal
Wolfgang Nebel, Univ. Oldenburg, Germany
Vassilis Paliouras, Univ. of Patras, Greece
Christian Piguet, CSEM, Switzerland
Manuel Prieto, Universidad Complutense de Madrid, Spain
Delong Shang, Newcastle University, UK
Gilles Sicard, Tima, Grenoble, France
Dimitrios Soudris, NTUA, Athens, Greece
Diederik Verkest, IMEC, Belgium
Alex Yakovlev, Newcastle University, UK
Roberto Zafalon, ST Microelectronics, Italy
Program committee
(to be confirmed)
Atila Alvandpour, Linköping Univ., Sweden
David Atienza, EPFL, Switzerland
Jose L Ayala, Spain
Nadine Azemard, Univ. Montpellier, France
Shlomo Beer, Technion, Israel
Peter Beerel, USC, USA
Luca Benini, Univ. Bologna, Italy
Mladen Berekovic, TU Braunschweig, Germany
Michaela Blott, Xilinx, Dublin
Joao Cardoso, Univ. of Porto, Portugal
Naehyuck Chang, Seoul Univ., Korea
Jorge Juan Chico, Univ. Sevilla, Spain
Ian Clark, NCU, UK
Martin Danek, UTIA AV CR, Czech Republic
Pedro Diniz, USC, USA
Tarek El-Ghazawi, GWU, USA
Joan Figueras, Univ. Catalunya, Spain
Alex Fish, Bar Ilan University, Israel
Eby Friedman, Univ. Rochester, USA
Alan D. George, University of Florida
Guy Gogniat, Bretagne-Sud University, France
Costas Goutis, Univ. Patras, Greece
Diana Göhringer, KIT, Germany
Eckhard Grass, IHP, Germany
Josés Luís Güntzel, Univ. Santa Catarina, Brazil
Oscar Gustafsson, Linköping Univ., Sweden
Domenik Helms, OFFIS research institute, Germany
Jörg Henkel, KIT, Germany
Shiyan Hu, Michigan Technical Univ., USA
Michael Hübner, RU Bochum, Germany
Nathalie Julien, Univ. Bretage-Sud, France
Rainer Kress, intel, Germany
Loïc Lagadec, University of Western Brittany, France
Rene van Leuken, TU Delft, Netherlands
Philippe Maurine, Univ. Montpellier, France
Elmar Melcher, UFCG, Campina Grande, PB, Brasil
Jose Monteiro, INESC-ID / IST, Portugal
Vasily Moshnyaga, Univ. Fukuoka, Japan
Tudor Murgan, Infineon, Germany
Wolfgang Nebel, Univ. Oldenburg, Germany
Dimitris Nikolos, Univ. Patras, Greece
Antonio Nunez, Univ. Las Palmas, Spain
Vojin Oklobdzija, Univ. Texas at Dallas, USA
Vassilis Paliouras, Univ. Patras, Greece
Davide Pandini, ST Microelectronics, Italy
Antonis Papanikolaou, NTUA, Greece
Christian Piguet, CSEM, Switzerland
Massimo Poncino, Politecnico Torino, Italy
Ricardo Reis, Univ. Porto Alegre, Brazil
Donatella Sciuto, Politecnico Milano, Italy
Delong Shang, NCU, UK
Dimitrios Soudris, NTUA, Athens, Greece
Jens Sparsö, Denmarks Technical University
Christer Svensson, Linkoping University, Sweden
Arnaud Tisserand, University of Rennes, France
Ingrid Verbauwhede, KU Leuven, Belgium
Flavio Wagner, UFRGS, Brasil
Robin Wilson, ST Microelectronics, France
Alex Yakovlev, NCU, UK
Zuochang Ye, Tsinghua Univ., Beijing, China
Submitted by Anonymous
on
The International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2013 is the 23nd in a series of international workshops. The PATMOS meeting has evolved into a leading scientific event where industry and academia meet to discuss power and timing aspects in modern integrated circuit and system design. Both Universities and Companies are invited to participate.
The PATMOS objective is to provide a forum to discuss and investigate emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems, including reconfigurable hardware such as FPGA’s. The technical program will focus on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization.
Topics of InterestAuthors are invited to submit manuscripts of original unpublished research. This year a focus is on power-efficiency. The topics of interest include, but are not limited to:
Reliability and Technology Variations
• Modeling and simulation in the presence of variability
• Variation-aware circuit design
• Reliability issues in nanoscale circuits
• Soft errors and radiation hardening
• Methods and Architectures for fault dependability
• Resilient hardware/software architectures
• Design for self adaptive circuits and systems
• Sensors for power, variability, temperature, and aging
Low Power and Thermal-aware Design
• Design techniques for thermal-aware and low power circuits and systems
• Power/thermal-aware synthesis and floorplanning
• Policies for power and thermal optimization
• Power/Thermal Estimation and Optimization
• Power/Thermal-aware architectures
• Hardware-software interaction for power/temperature minimization
• Energy-harvesting
• Low Power Systems: wireless sensor networks, mobile computing
Compilers, operating systems and runtime systems
• Power efficiency through parallelizing compilers or parallel programming
• Concepts for programming novel multi-core architectures
• Real-time system compilers, operating systems and run-time systems
FPGAs and GPU-based accelerators
• Novel accelerator-based architectures and architectural features
• High-Level Abstractions and CAD tools for using accelerators
• Neuro-Inspired Accelerators for Computing
• Customized processor instruction sets
• Compilers optimizing for dynamically reconfigurable processor arrays (DRPAs)
• Case studies and challenges on DRPAs and accelerators
Power-efficient High-performance ICT and Data Centers
• Supercomputing: compilers, operating systems, run time systems
• Hardware-software interaction for low power high-performance
• Modeling and analysis of energy costs for ICT subsystems and infrastructures
• Power analysis for data centers, supercomputers, communication networks
• Cross layer approaches and new paradigms for power efficiency in ICT
• Power-efficient I/O interfaces and NoC design
• Low power high performance in extreme scale supercomputing
• Heterogeneous HPC by new storage technologies
• Case studies: test cases, or design study challenges on data stations or supercomputers
Application-specific power efficiency by algorithmic and analytic efforts
• Banking, financial modeling and financial database acceleration
• Social networks, games, entertainment, ambient intelligence, ubiquitous and wearable computing
• Bioinformatics, bio-inspired, medical, and genetics systems and life sciences
• Physics and astronomy, weather prediction, oil and gas exploration, and more
• Security systems, cryptography, object recognition and tracking, global navigation satellite systems
• Audio/video, imaging, smart cameras, PDAs, smart image sensors, Reconfigurable Video Coding (RVC), etc. Aerospace, avionics, automotive and railway, and many other application areas
Case studies
• ICT, wireless sensor networks, wireless health, green computing, ultra low-power embedded systems, displays
• Examples, studies or challenges presenting innovative solutions for thermal and power efficiency
• Studies and experiences in using Azido
• Studies about power efficiency in extreme scale supercomputing projects
• Studies on energy efficiency by paradigm shift, by heterogeneous solutions or new storage technologies
• Case Studies on power efficiency of data stations
New directions in CS Education
• Roadmap of reconfigurable computing: compiled accelerators, ASICs and ASIPs
• New concepts in teaching, in tutorials, novel curricula and laboratories
• Industry and academic collaborative programs
• Design techniques for thermal and low power circuits and systems at all levels of abstraction
General co-chairs:
Jürgen Becker (becker@kit.edu)
Reiner Hartenstein (reiner@hartenstein.de)
Program co-chairs:
Jörg Henkel (henkel@kit.edu)
Alex Yakovlev ( Alex.Yakovlev@newcastle.ac.uk)
Publications chair:
Jian-Jia Chen (jian-jia.chen@kit.edu)
Publicity co-chairs:
Michael Hübner ( michael.huebner@rub.de)
Ricardo Reis ( reis@inf.ufrgs.br)
Local arrangements:
Lars Bauer (lars.bauer@kit.edu)
Oliver Sander (oliver.sander@kit.edu)
General chair VARI 2013:
Nadine Azemard (azemard@lirmm.fr)
Jörg Henkel (henkel@kit.edu)
Steering committee
Antonio J. Acosta, Univ. Sevilla, Spain
David Atienza, EPFL, Switzerland
Jose Luis Ayala, Universidad Complutense de Madrid, Spain
Nadine Azemard, Univ. Montpellier, France
Jürgen Becker Karlsruhe Institute of Technology, Germany
Joan Figueras, Univ. Catalunya, Spain
Reiner Hartenstein,TU Kaiserslautern, Germany
Jorge Juan-Chico, Univ. Sevilla, Spain
Rene van Leuken, TU Delft, The Netherlands
Enrico Macii, Politecnico di Torino, Italy
Philippe Maurine, Univ. Montpellier, France
Jose Monteiro, INESC-ID / IST, Portugal
Wolfgang Nebel, Univ. Oldenburg, Germany
Vassilis Paliouras, Univ. of Patras, Greece
Christian Piguet, CSEM, Switzerland
Manuel Prieto, Universidad Complutense de Madrid, Spain
Delong Shang, Newcastle University, UK
Gilles Sicard, Tima, Grenoble, France
Dimitrios Soudris, NTUA, Athens, Greece
Diederik Verkest, IMEC, Belgium
Alex Yakovlev, Newcastle University, UK
Roberto Zafalon, ST Microelectronics, Italy
Program committee
(to be confirmed)
Atila Alvandpour, Linköping Univ., Sweden
David Atienza, EPFL, Switzerland
Jose L Ayala, Spain
Nadine Azemard, Univ. Montpellier, France
Shlomo Beer, Technion, Israel
Peter Beerel, USC, USA
Luca Benini, Univ. Bologna, Italy
Mladen Berekovic, TU Braunschweig, Germany
Michaela Blott, Xilinx, Dublin
Joao Cardoso, Univ. of Porto, Portugal
Naehyuck Chang, Seoul Univ., Korea
Jorge Juan Chico, Univ. Sevilla, Spain
Ian Clark, NCU, UK
Martin Danek, UTIA AV CR, Czech Republic
Pedro Diniz, USC, USA
Tarek El-Ghazawi, GWU, USA
Joan Figueras, Univ. Catalunya, Spain
Alex Fish, Bar Ilan University, Israel
Eby Friedman, Univ. Rochester, USA
Alan D. George, University of Florida
Guy Gogniat, Bretagne-Sud University, France
Costas Goutis, Univ. Patras, Greece
Diana Göhringer, KIT, Germany
Eckhard Grass, IHP, Germany
Josés Luís Güntzel, Univ. Santa Catarina, Brazil
Oscar Gustafsson, Linköping Univ., Sweden
Domenik Helms, OFFIS research institute, Germany
Jörg Henkel, KIT, Germany
Shiyan Hu, Michigan Technical Univ., USA
Michael Hübner, RU Bochum, Germany
Nathalie Julien, Univ. Bretage-Sud, France
Rainer Kress, intel, Germany
Loïc Lagadec, University of Western Brittany, France
Rene van Leuken, TU Delft, Netherlands
Philippe Maurine, Univ. Montpellier, France
Elmar Melcher, UFCG, Campina Grande, PB, Brasil
Jose Monteiro, INESC-ID / IST, Portugal
Vasily Moshnyaga, Univ. Fukuoka, Japan
Tudor Murgan, Infineon, Germany
Wolfgang Nebel, Univ. Oldenburg, Germany
Dimitris Nikolos, Univ. Patras, Greece
Antonio Nunez, Univ. Las Palmas, Spain
Vojin Oklobdzija, Univ. Texas at Dallas, USA
Vassilis Paliouras, Univ. Patras, Greece
Davide Pandini, ST Microelectronics, Italy
Antonis Papanikolaou, NTUA, Greece
Christian Piguet, CSEM, Switzerland
Massimo Poncino, Politecnico Torino, Italy
Ricardo Reis, Univ. Porto Alegre, Brazil
Donatella Sciuto, Politecnico Milano, Italy
Delong Shang, NCU, UK
Dimitrios Soudris, NTUA, Athens, Greece
Jens Sparsö, Denmarks Technical University
Christer Svensson, Linkoping University, Sweden
Arnaud Tisserand, University of Rennes, France
Ingrid Verbauwhede, KU Leuven, Belgium
Flavio Wagner, UFRGS, Brasil
Robin Wilson, ST Microelectronics, France
Alex Yakovlev, NCU, UK
Zuochang Ye, Tsinghua Univ., Beijing, China