The objective of this research is to develop non-volatile computing devices, which allow the power source to be cut off at any time, and yet resume regular operation without loss of information when the power comes back. The approach is to replace all critical memory components with non-volatile units so that computing state is maintained over power interruptions. The advancement in new Flash memory devices makes this approach feasible by enabling low-voltage program/erase (P/E) around ±2V and a long (projected >1016) cycling endurance to be integrated into CMOS technology. This research effort seeks to establish a new paradigm of computing where non-volatile memory units are used pervasively to enhance reliability against power source instability, energy-efficiency, and security. The non-volatile computing devices are especially useful for embedded cyber-physical systems enabling long running computations and data collection even with unreliable power sources. The technologies developed from this project can also benefit conventional architecture in its power optimization and internal security code generation. The project is a close collaboration between computer architecture and CMOS technology development groups, where all levels in the design hierarchy will be visited for system and technology evaluation. This project integrates its research efforts with education by developing an undergraduate and Master curriculum that spans over the vertical design hierarchy in microprocessors. This vertical education will better prepare future work force in tackling tremendous design challenges spanning many layers of microprocessors. The results from this project will be made widely available to both industry and academia.