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Cyber-Physical Systems Virtual Organization
Fostering collaboration among CPS professionals in academia, government, and industry
CPS-VO
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biblio
How to Control a TCP: Minimally-Invasive Congestion Management for Datacenters
Submitted by grigby1 on Wed, 12/02/2020 - 1:01pm
bottleneck capacity
computer centres
coupled congestion control
Couplings
datacenter
guest OS
Hardware
hypervisor control traffic
internet
Internet-wide benefits
minimally-invasive congestion management
multitenant datacenters
operating systems (computers)
Proposals
pubcrawl
Receivers
reduced interflow competition
Registers
resilience
Resiliency
Scalability
Switches
TCP congestion control
TCP connections
TCP receiver window
TCP sending rate
telecommunication congestion control
telecommunication traffic
transport protocols
unequal share
Virtual machine monitors
virtual machines
biblio
Copker: A Cryptographic Engine Against Cold-Boot Attacks
Submitted by aekwall on Mon, 11/30/2020 - 11:08am
Internet of Things
private key cryptography
Kernel
Resiliency
pubcrawl
Cryptography
cyber physical systems
random number generation
Random access memory
RSA
Computers
Compositionality
Registers
memory data
cryptographic keys
sensitive information
deterministic random bit generator
private key
Cathode ray tubes
Cache-as-RAM
cold-boot attack
cold-boot attacks
Copker stores kilobytes
CPU registers
cryptographic engine
cryptographic services
deterministic random bit generators
disk encryption
ECDSA signing
key-encryption key
multiple private keys
on-chip CPU caches
PGP Email clients
plain-text sensitive data
popular asymmetric cryptosystems
public-key cryptography implementation
RAM chips
suspend mode
Magnetic Remanence
biblio
Low-Overhead Robust RTL Signature for DSP Core Protection: New Paradigm for Smart CE Design
Submitted by aekwall on Mon, 11/09/2020 - 12:41pm
IP networks
Hardware
Resiliency
pubcrawl
composability
policy-based governance
digital signatures
microprocessor chips
Multiplexing
Registers
digital signal processing chips
Finite impulse response filters
adders
logic circuits
logic design
Latches
Consumer electronics
FIR filter
FIR filters
IP piracy
flip-flops
covert signature embedding process
digital signal processor
DSP core protection
DSP-MP IP core
IP vendors
low-overhead robust RTL signature
Multimedia Processor
nonsignature FIR RTL design
register-transfer level
reusable Intellectual Property cores
robust IP owner
secured smart CE device
smart CE design
smart Consumer Electronics devices
biblio
DLockout: A Design Lockout Technique for Key Obfuscated RTL IP Designs
Submitted by aekwall on Mon, 11/09/2020 - 12:40pm
IP networks
Cryptography
Hardware
security
Software
Resiliency
pubcrawl
composability
policy-based governance
logic locking
Computer crime
process control
reverse engineering
Integrated circuit modeling
Registers
logic circuits
controller
IP piracy
applied key
common side-channel attacks
Datapath
datapath intensive IPs
Design Lockout
DLockout
key obfuscated RTL IP designs
key obfuscated RTL module
key obfuscation
key-based obfuscation techniques
legacy IP
nondestructive manner
obfuscation logic output
overproduction
robust design lockout technique
RTL Obfuscation
semiconductor supply chain
storage capacity 128 bit
storage capacity 32 bit
storage capacity 64 bit
typical design corner
biblio
SoCINT: Resilient System-on-Chip via Dynamic Intrusion Detection
Submitted by grigby1 on Mon, 11/02/2020 - 11:29am
composability
dynamic intrusion detection approach
field programmable gate arrays
FPGA platform
Hardware
Hardware Security
hardware tracing
Hardware Trojans
industrial property
intellectual properties
intellectual property security
Intrusion Detection
IP networks
Monitoring
open source processor
policy-based governance
pubcrawl
Registers
resilience
Resiliency
Runtime system
security
SoCINT
SoCs
software tools
system-on-chip
Trojan horses
biblio
A Graph Theory Approach towards IJTAG Security via Controlled Scan Chain Isolation
Submitted by grigby1 on Mon, 11/02/2020 - 11:28am
authorisation
Clocks
Complexity theory
composability
controlled scan chain isolation
data integrity
Data Integrity Attacks
data manipulation
data protection scheme
data sniffing
debug
design for test
Diagnosis
electronic design automation
embedded instruments
embedded systems
graph coloring problem
graph colouring
graph theory approach
hidden test-data registers
IEEE standards
IEEE Std 1687
IEEE Std. 1687
IJTAG
IJTAG network
IJTAG security
Instruments
intellectual property security
isolation signals
microprocessor chips
on-chip access
on-chip instruments
policy-based governance
power consumption
pubcrawl
Registers
resilience
Resiliency
scan chain
security
security of data
system-on-chip
system-on-chip designs
third party intellectual property providers
unauthorized user access
untrusted sources
biblio
Evolved Similarity Techniques in Malware Analysis
Submitted by aekwall on Mon, 10/26/2020 - 11:14am
Malware Analysis
graph theory
binary similarity
Databases
evolved code
evolved similarity techniques
function call graph
Human behavior
invasive software
malware
malware authors
malware evolution
malware family
malware function pairs
malware function similarity techniques
malware samples
malware similarity
Manuals
Metrics
Predictive Metrics
privacy
pubcrawl
Registers
Resiliency
reverse engineering
Semantics
Zeus
Zeus malware
biblio
QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment
Submitted by grigby1 on Fri, 09/18/2020 - 1:15pm
hardware description languages
Hardware design languages
Cryptography
security solutions
security of data
security
pubcrawl
Metrics
resilience
Resiliency
Hardware
Integrated circuit modeling
integrated circuit testing
Scalability
Registers
integrated circuit design
formal verification
Measurement
Compositionality
uncertainty
Vulnerability Analysis
electronic engineering computing
data flow
design mistakes
design stage
formal verification methods
hardware designer
hardware overhead
hardware system
hardware vulnerabilities
language based framework
language-based approach
language-based hardware security verification
malicious logic detection
potential security vulnerabilities
pre-silicon security assessment
promising solution
QIF model
QIF-Verilog
quantified information flow model
quantitative information-flow
security rules
verification process
Verilog type systems
vulnerable logic detection
compiler security
biblio
Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow
Submitted by grigby1 on Fri, 09/04/2020 - 3:16pm
Cryptography
encryption
Information Leakage
pubcrawl
composability
Metrics
Resiliency
resilience
sensitive data
Registers
AES
Probes
black-box model attack
countermeasures
dataflow
datapath components
dynamic random mapping
embedded cryptographic implementations
exploitable leakage
fixed S-box
fully controlled access
generic attack
high resolution EM probes
high-performance implementation
localized electromagnetic attack
localized EM attacks
minimum traces to disclosure
permutation network
potent threat
Power Attacks
profiled attack
randomization results
Semiconductor device measurement
side-channel attacks
spatial randomization
state register byte
transient random value
black box encryption
biblio
United We Stand: A Threshold Signature Scheme for Identifying Outliers in PLCs
Submitted by grigby1 on Fri, 09/04/2020 - 2:16pm
I-O Systems
i-o systems security
security
(k
\$-threshold signature scheme
Anomaly Detection
BIOS Security
compromised state
control engineering computing
corrupted PLC
cyber security awareness week-2017 competition
digital signatures
electro-mechanical processes
finite state machine
finite state machines
group-signature
Human Factors
I/O pin configuration attack
input-output mechanism
IO pin configuration attack
l)-threshold signature scheme
Legacy PLC system
legacy PLCs
malicious code
malicious disruption
malware
Metrics
OpenPLC software
particular state
Pins
PLCs
predefined states
programmable controllers
Protocols
Prototypes
pubcrawl
Pulse width modulation
pulse width modulation pins
PWM
Raspberry Pi
Registers
resilience
Resiliency
Scalability
signature shares
uncorrupted PLC
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