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Cyber-Physical Systems Virtual Organization
Fostering collaboration among CPS professionals in academia, government, and industry
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biblio
QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment
Submitted by
grigby1
on Fri, 09/18/2020 - 2:15pm
hardware description languages
Hardware design languages
Cryptography
security solutions
security of data
security
pubcrawl
Metrics
resilience
Resiliency
Hardware
Integrated circuit modeling
integrated circuit testing
Scalability
Registers
integrated circuit design
formal verification
Measurement
Compositionality
uncertainty
Vulnerability Analysis
electronic engineering computing
data flow
design mistakes
design stage
formal verification methods
hardware designer
hardware overhead
hardware system
hardware vulnerabilities
language based framework
language-based approach
language-based hardware security verification
malicious logic detection
potential security vulnerabilities
pre-silicon security assessment
promising solution
QIF model
QIF-Verilog
quantified information flow model
quantitative information-flow
security rules
verification process
Verilog type systems
vulnerable logic detection
compiler security
biblio
Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow
Submitted by
grigby1
on Fri, 09/04/2020 - 4:16pm
Cryptography
encryption
Information Leakage
pubcrawl
composability
Metrics
Resiliency
resilience
sensitive data
Registers
AES
Probes
black-box model attack
countermeasures
dataflow
datapath components
dynamic random mapping
embedded cryptographic implementations
exploitable leakage
fixed S-box
fully controlled access
generic attack
high resolution EM probes
high-performance implementation
localized electromagnetic attack
localized EM attacks
minimum traces to disclosure
permutation network
potent threat
Power Attacks
profiled attack
randomization results
Semiconductor device measurement
side-channel attacks
spatial randomization
state register byte
transient random value
black box encryption
biblio
United We Stand: A Threshold Signature Scheme for Identifying Outliers in PLCs
Submitted by
grigby1
on Fri, 09/04/2020 - 3:16pm
Protocols
Scalability
digital signatures
pubcrawl
Metrics
Resiliency
resilience
malicious code
malware
Human Factors
Anomaly Detection
control engineering computing
programmable controllers
Registers
(k
\$-threshold signature scheme
compromised state
corrupted PLC
cyber security awareness week-2017 competition
electro-mechanical processes
finite state machine
finite state machines
group-signature
I/O pin configuration attack
input-output mechanism
IO pin configuration attack
l)-threshold signature scheme
Legacy PLC system
legacy PLCs
malicious disruption
OpenPLC software
particular state
Pins
PLCs
predefined states
Prototypes
Pulse width modulation
pulse width modulation pins
PWM
Raspberry Pi
signature shares
uncorrupted PLC
BIOS Security
biblio
Identification of State Registers of FSM Through Full Scan by Data Analytics
Submitted by
grigby1
on Fri, 08/28/2020 - 3:55pm
logic design
data analysis
Data mining
pubcrawl
Resiliency
industrial property
Scalability
Big Data
Decision trees
Registers
Data protection
finite state machines
resilience
Silicon
regression analysis
electronic engineering computing
Intellectual Property Protection
Big Data Analytics
Decision Tree
downstream design
finite-state machine
FSM design
FSM state registers
OpenCores
Physical design
state register identification
state transitions
big data security metrics
biblio
Reusable intellectual property core protection for both buyer and seller
Submitted by
grigby1
on Thu, 07/30/2020 - 2:05pm
logic circuits
logic design
IP networks
pubcrawl
Human behavior
Human Factors
policy-based governance
resilience
Resiliency
microprocessor chips
embedded systems
composability
Registers
Fingerprint recognition
Metrics
resource management
intellectual property
Watermarking
ip protection
architectural synthesis process
buyer fingerprint
CE devices
Consumer electronics
design cost overhead
IP core design
IP core protection
IP seller
latency overhead
register allocation phase
reusable intellectual property core protection
scheduling phase
seller watermark
biblio
A Modeling Attack Resistant Deception Technique for Securing PUF based Authentication
Submitted by
grigby1
on Fri, 06/19/2020 - 11:49am
active deception protocol
attack resistant deception technique
authentic CRP
authentication
authentication protocol
binary channel
Buildings
challenge response pairs
Cryptographic Protocols
false PUF multiplexing
false trust
Generators
learning (artificial intelligence)
machine learning attacks
ML attack
Multiplexing
mutual authentication
physical unclonable function (PUF)
physical unclonable function-based authentication protocol
policy-based governance
Policy-Governed Secure Collaboration
Protocols
pubcrawl
PUF-based authentication method
Registers
replay attacks
resilience
Resiliency
Resistance
resource-rich server authentication
Scalability
Servers
biblio
Fast Reconfigurable Hash Functions for Network Flow Hashing in FPGAs
Submitted by
grigby1
on Fri, 06/12/2020 - 12:09pm
Compositionality
Cryptography
fast reconfigurable hash functions
field programmable gate array
field programmable gate arrays
FPGA
genetic algorithms
genetic programming
Hardware
hardware acceleration
hash algorithms
hash function design
high speed computer networks
high-quality hash functions
IP networks
Linear programming
Monitoring
multiobjective linear genetic programming
network flow hashing
pubcrawl
reconfigurable architectures
reconfigurable design
reconfigurable hash function
Registers
resilience
Resiliency
biblio
Enhanced Secure Hash Algorithm-512 based on Quadratic Function
Submitted by
grigby1
on Fri, 06/12/2020 - 12:09pm
avalanche effect
Compositionality
Cryptography
enhanced secure hash algorithm-512
enhanced SHA-1 algorithm
extended bits
hash algorithms
hash collision
hash collisions
Hash functions
hash message
hash outputs
mobile ad hoc networks
password
primitive function
pubcrawl
quadratic function
Registers
resilience
Resiliency
SHA-1
Urban areas
biblio
A Kernel Rootkit Detection Approach Based on Virtualization and Machine Learning
Submitted by
grigby1
on Fri, 04/17/2020 - 11:28am
composability
feature extraction
Hardware
hardware assisted virtualization technology
invasive software
Kernel
kernel rootkit
kernel rootkit detection approach
kernel rootkit detection solution
kernel rootkit detection system
kernel space
learning (artificial intelligence)
machine learning
machine learning techniques
malicious kernel module
Metrics
operating system
operating system kernels
operating systems (computers)
OS
OS kernel
OS resource management
pubcrawl
Registers
resilience
Resiliency
rootkit
run-time features
security of data
system monitoring
target kernel module
TF-IDF method
user-mode rootkit detection
Virtual machine monitors
virtual machines
virtualisation
Virtualization
windows kernel rootkits
Windows Operating System Security
biblio
HyperPS: A Hypervisor Monitoring Approach Based on Privilege Separation
Submitted by
grigby1
on Fri, 03/27/2020 - 11:28am
Cloud Computing
cloud environment
collaboration
guest virtual machine security
Human behavior
Human Factors
HyperPS
hypervisor monitoring
hypervisor security
Kernel
KVM hypervisor
Linux
Logic gates
Metrics
microhypervisor reducing attack surface
Monitoring
monolithic operating system
operating system kernels
policy-based governance
privilege separation
pubcrawl
Registers
resilience
Resiliency
Safe Coding
security
security of data
security-sensitive system resources
system monitoring
system software error
Trusted Computing
trusted environment
Virtual machine monitors
virtual machines
Virtualization
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